From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>,
Peter Maydell <peter.maydell@linaro.org>
Cc: Dorjoy Chowdhury <dorjoychy111@gmail.com>,
qemu-devel@nongnu.org, Leif Lindholm <quic_llindhol@quicinc.com>
Subject: Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT
Date: Wed, 1 May 2024 20:08:05 +0200 [thread overview]
Message-ID: <cb2d4f21-8853-47af-a78f-e0db65460f46@linaro.org> (raw)
In-Reply-To: <753b3a55-9589-4dcb-b656-8b3025e847df@linaro.org>
W dniu 22.04.2024 o 17:21, Richard Henderson pisze:
>>> For Arm's CPUs they fall into two categories:
>>> * older ones don't set MT in their MPIDR, and the Aff0
>>> field is effectively the CPU number
>>> * newer ones do set MT in their MPIDR, but don't have
>>> SMT, so their Aff0 is always 0 and their Aff1
>>> is the CPU number
>>>
>>> Of all the CPUs we model, none of them are the
>>> architecturally-permitted "MT is set, CPU implements
>>> actual SMT, Aff0 indicates the thread in the CPU" type.
>>
>> Looking at the TRM, Neoverse-E1 is "MT is set, actual SMT,
>> Aff0 is the thread" (Aff0 can be 0 or 1). We just don't
>> model that CPU type yet. But we should probably make
>> sure we don't block ourselves into a corner where that
>> would be awkward -- I'll have a think about this and
>> look at what x86 does with the topology info.
>
> I'm suggesting that we set things up per -smp, and if the user chooses a
> -cpu value for which that topology doesn't make sense, we do it anyway
> and let them keep both pieces.
Aff[0-3] are 8 bit each. On those cpus where they exist.
So "-smp 512" (maximum allowed for sbsa-ref) would need to be split to 2
clusters by 256 cores or 64 clusters of 8 cores each like it is today so
it is backward compatible with whatever assumption firmware/OS does.
But if we go for 'newer, better MPIDR_EL1' then maybe it is time to set
U bit [30] if "-smp X,sockets=Y" where Y > 1? Or when NUMA config with
multiple cpu nodes are setup.
Also a way to know which AffX fields to check on firmware/OS side would
be nice. A57/72 use Aff[1-2], N1+ use Aff[0-3]. Sure, it can be checked
by going through cores, reading then MPIDR_EL1 and if 7:0 has same value
on all of them then check Aff[1-3], otherwise Aff[1-2].
next prev parent reply other threads:[~2024-05-01 18:09 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-19 18:31 [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT Dorjoy Chowdhury
2024-04-21 5:40 ` Richard Henderson
2024-04-21 8:40 ` Dorjoy Chowdhury
2024-04-22 10:46 ` Peter Maydell
2024-04-22 11:26 ` Peter Maydell
2024-04-22 15:21 ` Richard Henderson
2024-04-22 15:24 ` Richard Henderson
2024-05-01 18:08 ` Marcin Juszkiewicz [this message]
2024-05-02 9:11 ` Peter Maydell
2024-05-02 10:37 ` Peter Maydell
2024-05-02 10:56 ` Marcin Juszkiewicz
2024-05-02 11:40 ` Peter Maydell
2024-04-25 16:46 ` Dorjoy Chowdhury
2024-05-02 12:14 ` Marcin Juszkiewicz
2024-05-02 13:04 ` Dorjoy Chowdhury
2024-05-02 13:11 ` Marcin Juszkiewicz
2024-05-02 13:13 ` Peter Maydell
2024-05-02 13:50 ` Marcin Juszkiewicz
2024-05-02 13:57 ` Peter Maydell
2024-05-03 16:28 ` Peter Maydell
2024-05-03 16:52 ` Dorjoy Chowdhury
2024-05-31 12:52 ` Peter Maydell
2024-05-31 13:46 ` Dorjoy Chowdhury
2024-05-03 18:14 ` Dorjoy Chowdhury
2024-05-04 13:31 ` Peter Maydell
2024-05-04 14:20 ` Dorjoy Chowdhury
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