From: Dorjoy Chowdhury <dorjoychy111@gmail.com>
To: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org
Subject: Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT
Date: Thu, 2 May 2024 19:04:18 +0600 [thread overview]
Message-ID: <CAFfO_h6-RXettxqnCYciDrq6ivsTHtM55FcksJSUNnLdbio4mg@mail.gmail.com> (raw)
In-Reply-To: <7c6f66bf-2610-494c-9389-b558a11f8c5f@linaro.org>
On Thu, May 2, 2024 at 6:14 PM Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> W dniu 19.04.2024 o 20:31, Dorjoy Chowdhury pisze:
> > -uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
> > +uint64_t arm_build_mp_affinity(ARMCPU *cpu, int idx, uint8_t clustersz)
> > {
> > + if (cpu->has_smt) {
> > + /*
> > + * Right now, the ARM CPUs with SMT supported by QEMU only have
> > + * one thread per core. So Aff0 is always 0.
> > + */
> > + uint32_t Aff2 = idx / clustersz;
> > + uint32_t Aff1 = idx % clustersz;
> > + uint32_t Aff0 = 0;
> > + return (Aff2 << ARM_AFF2_SHIFT) | (Aff1 << ARM_AFF1_SHIFT) | Aff0;
> > + }
>
> Should "return" also have "(1 << 24) |" to have MT=1 set?
>
> Otherwise MPIDR_EL1 = 0x000100 can mean core0 in cluster1 or core1 in
> cluster0.
>
> Value 0x1000100 shows MT=1 so thread0 in core1 in cluster0.
I don't know all the details but from what I understand the
"arm_build_mp_afiinity" is used to set the "mp_affinity" member
variable which I assume is about affinity, not the whole MPIDR
register value. That is what I assumed because the Uniprocessor
indication bit(30) is being set only in the "mpidr_read_val" function.
In the patch, the MT bit is also being set in the "mpidr_read_val"
function based on the SMT status (has_smt) of the CPU.
Regards,
Dorjoy
next prev parent reply other threads:[~2024-05-02 13:05 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-19 18:31 [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT Dorjoy Chowdhury
2024-04-21 5:40 ` Richard Henderson
2024-04-21 8:40 ` Dorjoy Chowdhury
2024-04-22 10:46 ` Peter Maydell
2024-04-22 11:26 ` Peter Maydell
2024-04-22 15:21 ` Richard Henderson
2024-04-22 15:24 ` Richard Henderson
2024-05-01 18:08 ` Marcin Juszkiewicz
2024-05-02 9:11 ` Peter Maydell
2024-05-02 10:37 ` Peter Maydell
2024-05-02 10:56 ` Marcin Juszkiewicz
2024-05-02 11:40 ` Peter Maydell
2024-04-25 16:46 ` Dorjoy Chowdhury
2024-05-02 12:14 ` Marcin Juszkiewicz
2024-05-02 13:04 ` Dorjoy Chowdhury [this message]
2024-05-02 13:11 ` Marcin Juszkiewicz
2024-05-02 13:13 ` Peter Maydell
2024-05-02 13:50 ` Marcin Juszkiewicz
2024-05-02 13:57 ` Peter Maydell
2024-05-03 16:28 ` Peter Maydell
2024-05-03 16:52 ` Dorjoy Chowdhury
2024-05-31 12:52 ` Peter Maydell
2024-05-31 13:46 ` Dorjoy Chowdhury
2024-05-03 18:14 ` Dorjoy Chowdhury
2024-05-04 13:31 ` Peter Maydell
2024-05-04 14:20 ` Dorjoy Chowdhury
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