From: Peter Maydell <peter.maydell@linaro.org>
To: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>,
Dorjoy Chowdhury <dorjoychy111@gmail.com>,
qemu-devel@nongnu.org, Leif Lindholm <quic_llindhol@quicinc.com>
Subject: Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT
Date: Thu, 2 May 2024 12:40:43 +0100 [thread overview]
Message-ID: <CAFEAcA-mwRWTe_getRR5Ap3ycY+BvpyyVuCOFQABHvJMWv5KgA@mail.gmail.com> (raw)
In-Reply-To: <5da6dcc6-2c00-483f-bf33-cbeb3d931f2e@linaro.org>
On Thu, 2 May 2024 at 11:56, Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> W dniu 2.05.2024 o 12:37, Peter Maydell pisze:
> >> * what are the constraints on the Aff* fields (eg that kernel
> >> commit suggests Aff0 shouldn't be > 15)?
>
> > This one is apparently related to GICv3 -- if the GIC doesn't
> > implement RangeSelector support in ICC_SGI0R_EL1 and other
> > places (advertised via GICD_TYPER.RSS and ICC_CTLR_EL1.SS) then
> > there's no way to send an SGI to a CPU whose Aff0 is outside
> > [0..15], and so you shouldn't build a system with Aff0 > 15.
> > QEMU's GICv3 doesn't implement the RSS functionality (though it
> > wouldn't be hard to add if we really cared), so we should also
> > keep Aff0 in [0..15].
>
> Arm/virt uses 8 cores/cluster on GICv2 and 16 cores/cluster on GICv3 as
> this is amount of SGI target-list bits available.
You can't have more than 8 cores full stop on GICv2, though,
so you'll never be able to go beyond 8 cores/cluster
even if we didn't impose that limit.
-- PMM
next prev parent reply other threads:[~2024-05-02 11:41 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-19 18:31 [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT Dorjoy Chowdhury
2024-04-21 5:40 ` Richard Henderson
2024-04-21 8:40 ` Dorjoy Chowdhury
2024-04-22 10:46 ` Peter Maydell
2024-04-22 11:26 ` Peter Maydell
2024-04-22 15:21 ` Richard Henderson
2024-04-22 15:24 ` Richard Henderson
2024-05-01 18:08 ` Marcin Juszkiewicz
2024-05-02 9:11 ` Peter Maydell
2024-05-02 10:37 ` Peter Maydell
2024-05-02 10:56 ` Marcin Juszkiewicz
2024-05-02 11:40 ` Peter Maydell [this message]
2024-04-25 16:46 ` Dorjoy Chowdhury
2024-05-02 12:14 ` Marcin Juszkiewicz
2024-05-02 13:04 ` Dorjoy Chowdhury
2024-05-02 13:11 ` Marcin Juszkiewicz
2024-05-02 13:13 ` Peter Maydell
2024-05-02 13:50 ` Marcin Juszkiewicz
2024-05-02 13:57 ` Peter Maydell
2024-05-03 16:28 ` Peter Maydell
2024-05-03 16:52 ` Dorjoy Chowdhury
2024-05-31 12:52 ` Peter Maydell
2024-05-31 13:46 ` Dorjoy Chowdhury
2024-05-03 18:14 ` Dorjoy Chowdhury
2024-05-04 13:31 ` Peter Maydell
2024-05-04 14:20 ` Dorjoy Chowdhury
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