From: Anup Patel <anup@brainfault.org> To: Marc Zyngier <maz@kernel.org> Cc: Anup Patel <anup.patel@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, DTML <devicetree@vger.kernel.org> Subject: Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver Date: Mon, 14 Jun 2021 18:43:25 +0530 [thread overview] Message-ID: <CAAhSdy0jZTqZ+zTazpQLeCnbAHr99t40vEa-_GD0_UjBZsXWzg@mail.gmail.com> (raw) In-Reply-To: <87a6nsrdkm.wl-maz@kernel.org> On Mon, Jun 14, 2021 at 3:08 PM Marc Zyngier <maz@kernel.org> wrote: > > On Sun, 13 Jun 2021 13:25:40 +0100, > Anup Patel <anup@brainfault.org> wrote: > > > > On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > I'm sorry, but this really isn't an irqchip driver. This is a piece of > > > arch-specific code that uses *none* of the irq subsystem abstractions > > > apart from the IRQCHIP_DECLARE() macro. > > > > Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH. > > > > Both ACLINT MSWI and SSWI are special devices providing only IPI > > support so I will re-think how to fit this. > > It depends on how you think of IPIs in your architecture. > > arm64 (and even now 32bit) have been moved to a mode where IPIs are > normal interrupts, as it helps with other things such as our pseudo > NMIs, and reduces code duplication. MIPS has done the same for a long > time (they don't have dedicated HW for that). RISC-V is also moving in a similar direction with the RISC-V advanced interrupt architecture (AIA) specification which aims at defining an interrupt controller having MSI support, virtualization support and scalable for a large number of CPUs. The RISC-V AIA treats IPIs as normal interrupts. The RISC-V ACLINT based IPI support is for RISC-V systems which only need a simple interrupt controller without MSI support and virtualization support. These systems will not implement RISC-V AIA. Regards, Anup > > M. > > -- > Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Marc Zyngier <maz@kernel.org> Cc: Anup Patel <anup.patel@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, DTML <devicetree@vger.kernel.org> Subject: Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver Date: Mon, 14 Jun 2021 18:43:25 +0530 [thread overview] Message-ID: <CAAhSdy0jZTqZ+zTazpQLeCnbAHr99t40vEa-_GD0_UjBZsXWzg@mail.gmail.com> (raw) In-Reply-To: <87a6nsrdkm.wl-maz@kernel.org> On Mon, Jun 14, 2021 at 3:08 PM Marc Zyngier <maz@kernel.org> wrote: > > On Sun, 13 Jun 2021 13:25:40 +0100, > Anup Patel <anup@brainfault.org> wrote: > > > > On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > I'm sorry, but this really isn't an irqchip driver. This is a piece of > > > arch-specific code that uses *none* of the irq subsystem abstractions > > > apart from the IRQCHIP_DECLARE() macro. > > > > Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH. > > > > Both ACLINT MSWI and SSWI are special devices providing only IPI > > support so I will re-think how to fit this. > > It depends on how you think of IPIs in your architecture. > > arm64 (and even now 32bit) have been moved to a mode where IPIs are > normal interrupts, as it helps with other things such as our pseudo > NMIs, and reduces code duplication. MIPS has done the same for a long > time (they don't have dedicated HW for that). RISC-V is also moving in a similar direction with the RISC-V advanced interrupt architecture (AIA) specification which aims at defining an interrupt controller having MSI support, virtualization support and scalable for a large number of CPUs. The RISC-V AIA treats IPIs as normal interrupts. The RISC-V ACLINT based IPI support is for RISC-V systems which only need a simple interrupt controller without MSI support and virtualization support. These systems will not implement RISC-V AIA. Regards, Anup > > M. > > -- > Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2021-06-14 13:14 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-12 16:04 [RFC PATCH v1 00/10] RISC-V ACLINT Support Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-12 16:04 ` [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:33 ` Bin Meng 2021-06-14 13:33 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:33 ` Bin Meng 2021-06-14 13:33 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 03/10] RISC-V: Allow more details in IPI operations Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-12 16:04 ` [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-13 9:33 ` Marc Zyngier 2021-06-13 9:33 ` Marc Zyngier 2021-06-13 12:28 ` Anup Patel 2021-06-13 12:28 ` Anup Patel 2021-06-12 16:04 ` [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-13 9:41 ` Marc Zyngier 2021-06-13 9:41 ` Marc Zyngier 2021-06-13 12:25 ` Anup Patel 2021-06-13 12:25 ` Anup Patel 2021-06-14 9:38 ` Marc Zyngier 2021-06-14 9:38 ` Marc Zyngier 2021-06-14 13:13 ` Anup Patel [this message] 2021-06-14 13:13 ` Anup Patel 2021-06-12 16:04 ` [RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng 2021-06-24 19:37 ` Rob Herring 2021-06-24 19:37 ` Rob Herring 2021-06-12 16:04 ` [RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng
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