All the mail mirrored from lore.kernel.org
 help / color / mirror / Atom feed
From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>
Subject: [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations
Date: Sat, 12 Jun 2021 21:34:13 +0530	[thread overview]
Message-ID: <20210612160422.330705-2-anup.patel@wdc.com> (raw)
In-Reply-To: <20210612160422.330705-1-anup.patel@wdc.com>

The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but readonly for M-mode so we clear this bit only when using
SBI IPI operations.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/kernel/sbi.c | 8 +++++++-
 arch/riscv/kernel/smp.c | 2 --
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 9a84f0cb5175..8aeca26198f2 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -598,8 +598,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
 	sbi_send_ipi(cpumask_bits(&hartid_mask));
 }
 
+static void sbi_ipi_clear(void)
+{
+	csr_clear(CSR_IP, IE_SIE);
+}
+
 static const struct riscv_ipi_ops sbi_ipi_ops = {
-	.ipi_inject = sbi_send_cpumask_ipi
+	.ipi_inject = sbi_send_cpumask_ipi,
+	.ipi_clear = sbi_ipi_clear
 };
 
 void __init sbi_init(void)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 921d9d7df400..547dc508f7d1 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -99,8 +99,6 @@ void riscv_clear_ipi(void)
 {
 	if (ipi_ops && ipi_ops->ipi_clear)
 		ipi_ops->ipi_clear();
-
-	csr_clear(CSR_IP, IE_SIE);
 }
 EXPORT_SYMBOL_GPL(riscv_clear_ipi);
 
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>
Subject: [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations
Date: Sat, 12 Jun 2021 21:34:13 +0530	[thread overview]
Message-ID: <20210612160422.330705-2-anup.patel@wdc.com> (raw)
In-Reply-To: <20210612160422.330705-1-anup.patel@wdc.com>

The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but readonly for M-mode so we clear this bit only when using
SBI IPI operations.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/kernel/sbi.c | 8 +++++++-
 arch/riscv/kernel/smp.c | 2 --
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 9a84f0cb5175..8aeca26198f2 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -598,8 +598,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
 	sbi_send_ipi(cpumask_bits(&hartid_mask));
 }
 
+static void sbi_ipi_clear(void)
+{
+	csr_clear(CSR_IP, IE_SIE);
+}
+
 static const struct riscv_ipi_ops sbi_ipi_ops = {
-	.ipi_inject = sbi_send_cpumask_ipi
+	.ipi_inject = sbi_send_cpumask_ipi,
+	.ipi_clear = sbi_ipi_clear
 };
 
 void __init sbi_init(void)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 921d9d7df400..547dc508f7d1 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -99,8 +99,6 @@ void riscv_clear_ipi(void)
 {
 	if (ipi_ops && ipi_ops->ipi_clear)
 		ipi_ops->ipi_clear();
-
-	csr_clear(CSR_IP, IE_SIE);
 }
 EXPORT_SYMBOL_GPL(riscv_clear_ipi);
 
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2021-06-12 16:05 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-12 16:04 [RFC PATCH v1 00/10] RISC-V ACLINT Support Anup Patel
2021-06-12 16:04 ` Anup Patel
2021-06-12 16:04 ` Anup Patel [this message]
2021-06-12 16:04   ` [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2021-06-14 13:33   ` Bin Meng
2021-06-14 13:33     ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-14 13:33   ` Bin Meng
2021-06-14 13:33     ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 03/10] RISC-V: Allow more details in IPI operations Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-13  9:33   ` Marc Zyngier
2021-06-13  9:33     ` Marc Zyngier
2021-06-13 12:28     ` Anup Patel
2021-06-13 12:28       ` Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-13  9:41   ` Marc Zyngier
2021-06-13  9:41     ` Marc Zyngier
2021-06-13 12:25     ` Anup Patel
2021-06-13 12:25       ` Anup Patel
2021-06-14  9:38       ` Marc Zyngier
2021-06-14  9:38         ` Marc Zyngier
2021-06-14 13:13         ` Anup Patel
2021-06-14 13:13           ` Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-14 13:34   ` Bin Meng
2021-06-14 13:34     ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-14 13:34   ` Bin Meng
2021-06-14 13:34     ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-14 13:34   ` Bin Meng
2021-06-14 13:34     ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-14 13:34   ` Bin Meng
2021-06-14 13:34     ` Bin Meng
2021-06-24 19:37   ` Rob Herring
2021-06-24 19:37     ` Rob Herring
2021-06-12 16:04 ` [RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel
2021-06-12 16:04   ` Anup Patel
2021-06-14 13:34   ` Bin Meng
2021-06-14 13:34     ` Bin Meng

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210612160422.330705-2-anup.patel@wdc.com \
    --to=anup.patel@wdc.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=anup@brainfault.org \
    --cc=atish.patra@wdc.com \
    --cc=daniel.lezcano@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=maz@kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=palmerdabbelt@google.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.