From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com> Subject: [RFC PATCH v1 00/10] RISC-V ACLINT Support Date: Sat, 12 Jun 2021 21:34:12 +0530 [thread overview] Message-ID: <20210612160422.330705-1-anup.patel@wdc.com> (raw) Most of the existing RISC-V platforms use SiFive CLINT to provide M-level timer and IPI support whereas S-level uses SBI calls for timer and IPI support. Also, the SiFive CLINT device is a single device providing both timer and IPI functionality so RISC-V platforms can't partially implement SiFive CLINT device and provide alternate mechanism for timer and IPI. The RISC-V Advacned Core Local Interruptor (ACLINT) tries to address the limitations of SiFive CLINT by: 1) Taking modular approach and defining timer and IPI functionality as separate devices so that RISC-V platforms can include only required devices 2) Providing dedicated MMIO device for S-level IPIs so that SBI calls can be avoided for IPIs in Linux RISC-V 3) Allowing multiple instances of timer and IPI devices for a multi-socket (or multi-die) NUMA systems 4) Being backward compatible to SiFive CLINT so that existing RISC-V platforms stay compliant with RISC-V ACLINT specification Latest RISC-V ACLINT specification (will be frozen in a month) can be found at: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc This series adds RISC-V ACLINT support and can be found in riscv_aclint_v1 branch at: https://github.com/avpatel/linux To test this series, the RISC-V ACLINT support for QEMU and OpenSBI can be found in the riscv_aclint_v1 branch at: https://github.com/avpatel/qemu https://github.com/avpatel/opensbi Anup Patel (10): RISC-V: Clear SIP bit only when using SBI IPI operations RISC-V: Use common print prefix in smp.c RISC-V: Allow more details in IPI operations RISC-V: Use IPIs for remote TLB flush when possible irqchip: Add ACLINT software interrupt driver RISC-V: Select ACLINT SWI driver for virt machine clocksource: clint: Add support for ACLINT MTIMER device dt-bindings: timer: Add ACLINT MTIMER bindings dt-bindings: timer: Add ACLINT MSWI and SSWI bindings MAINTAINERS: Add entry for RISC-V ACLINT drivers .../riscv,aclint-swi.yaml | 82 ++++++++++++ .../bindings/timer/riscv,aclint-mtimer.yaml | 55 ++++++++ MAINTAINERS | 9 ++ arch/riscv/Kconfig.socs | 1 + arch/riscv/include/asm/smp.h | 15 +++ arch/riscv/kernel/sbi.c | 10 +- arch/riscv/kernel/smp.c | 36 +++++- arch/riscv/mm/cacheflush.c | 2 +- arch/riscv/mm/tlbflush.c | 62 +++++++-- drivers/clocksource/timer-clint.c | 45 +++++-- drivers/irqchip/Kconfig | 11 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aclint-swi.c | 122 ++++++++++++++++++ 13 files changed, 415 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml create mode 100644 drivers/irqchip/irq-aclint-swi.c -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com> Subject: [RFC PATCH v1 00/10] RISC-V ACLINT Support Date: Sat, 12 Jun 2021 21:34:12 +0530 [thread overview] Message-ID: <20210612160422.330705-1-anup.patel@wdc.com> (raw) Most of the existing RISC-V platforms use SiFive CLINT to provide M-level timer and IPI support whereas S-level uses SBI calls for timer and IPI support. Also, the SiFive CLINT device is a single device providing both timer and IPI functionality so RISC-V platforms can't partially implement SiFive CLINT device and provide alternate mechanism for timer and IPI. The RISC-V Advacned Core Local Interruptor (ACLINT) tries to address the limitations of SiFive CLINT by: 1) Taking modular approach and defining timer and IPI functionality as separate devices so that RISC-V platforms can include only required devices 2) Providing dedicated MMIO device for S-level IPIs so that SBI calls can be avoided for IPIs in Linux RISC-V 3) Allowing multiple instances of timer and IPI devices for a multi-socket (or multi-die) NUMA systems 4) Being backward compatible to SiFive CLINT so that existing RISC-V platforms stay compliant with RISC-V ACLINT specification Latest RISC-V ACLINT specification (will be frozen in a month) can be found at: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc This series adds RISC-V ACLINT support and can be found in riscv_aclint_v1 branch at: https://github.com/avpatel/linux To test this series, the RISC-V ACLINT support for QEMU and OpenSBI can be found in the riscv_aclint_v1 branch at: https://github.com/avpatel/qemu https://github.com/avpatel/opensbi Anup Patel (10): RISC-V: Clear SIP bit only when using SBI IPI operations RISC-V: Use common print prefix in smp.c RISC-V: Allow more details in IPI operations RISC-V: Use IPIs for remote TLB flush when possible irqchip: Add ACLINT software interrupt driver RISC-V: Select ACLINT SWI driver for virt machine clocksource: clint: Add support for ACLINT MTIMER device dt-bindings: timer: Add ACLINT MTIMER bindings dt-bindings: timer: Add ACLINT MSWI and SSWI bindings MAINTAINERS: Add entry for RISC-V ACLINT drivers .../riscv,aclint-swi.yaml | 82 ++++++++++++ .../bindings/timer/riscv,aclint-mtimer.yaml | 55 ++++++++ MAINTAINERS | 9 ++ arch/riscv/Kconfig.socs | 1 + arch/riscv/include/asm/smp.h | 15 +++ arch/riscv/kernel/sbi.c | 10 +- arch/riscv/kernel/smp.c | 36 +++++- arch/riscv/mm/cacheflush.c | 2 +- arch/riscv/mm/tlbflush.c | 62 +++++++-- drivers/clocksource/timer-clint.c | 45 +++++-- drivers/irqchip/Kconfig | 11 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aclint-swi.c | 122 ++++++++++++++++++ 13 files changed, 415 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml create mode 100644 drivers/irqchip/irq-aclint-swi.c -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2021-06-12 16:05 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-12 16:04 Anup Patel [this message] 2021-06-12 16:04 ` [RFC PATCH v1 00/10] RISC-V ACLINT Support Anup Patel 2021-06-12 16:04 ` [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:33 ` Bin Meng 2021-06-14 13:33 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:33 ` Bin Meng 2021-06-14 13:33 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 03/10] RISC-V: Allow more details in IPI operations Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-12 16:04 ` [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-13 9:33 ` Marc Zyngier 2021-06-13 9:33 ` Marc Zyngier 2021-06-13 12:28 ` Anup Patel 2021-06-13 12:28 ` Anup Patel 2021-06-12 16:04 ` [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-13 9:41 ` Marc Zyngier 2021-06-13 9:41 ` Marc Zyngier 2021-06-13 12:25 ` Anup Patel 2021-06-13 12:25 ` Anup Patel 2021-06-14 9:38 ` Marc Zyngier 2021-06-14 9:38 ` Marc Zyngier 2021-06-14 13:13 ` Anup Patel 2021-06-14 13:13 ` Anup Patel 2021-06-12 16:04 ` [RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng 2021-06-12 16:04 ` [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng 2021-06-24 19:37 ` Rob Herring 2021-06-24 19:37 ` Rob Herring 2021-06-12 16:04 ` [RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel 2021-06-12 16:04 ` Anup Patel 2021-06-14 13:34 ` Bin Meng 2021-06-14 13:34 ` Bin Meng
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