Re: [PATCH v3 2/4] PCI: of: Relax the condition for warning about non-prefetchable memory aperture size

From: Vidya Sagar <vidyas@nvidia.com>
To: Punit Agrawal <punitagrawal@gmail.com>, <helgaas@kernel.org>,
	<robh+dt@kernel.org>
Cc: <linux-rockchip@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<alexandru.elisei@arm.com>, <wqu@suse.com>,
	<robin.murphy@arm.com>, <pgwipeout@gmail.com>, <ardb@kernel.org>,
	<briannorris@chromium.org>, <shawn.lin@rock-chips.com>
Subject: Re: [PATCH v3 2/4] PCI: of: Relax the condition for warning about non-prefetchable memory aperture size
Date: Wed, 9 Jun 2021 00:36:08 +0530	[thread overview]
Message-ID: <ac6bf3c8-fe8e-5897-b225-699a7c46a818@nvidia.com> (raw)
In-Reply-To: <20210607112856.3499682-3-punitagrawal@gmail.com>


On 6/7/2021 4:58 PM, Punit Agrawal wrote:
> External email: Use caution opening links or attachments
> 
> 
> Commit fede8526cc48 ("PCI: of: Warn if non-prefetchable memory
> aperture size is > 32-bit") introduced a warning for non-prefetchable
> resources that need more than 32bits to resolve. It turns out that the
> check is too restrictive and should be applicable to only resources
> that are limited to host bridge windows that don't have the ability to
> map 64-bit address space.
I think the host bridge windows having the ability to map 64-bit address 
space is different from restricting the non-prefetchable memory aperture 
size to 32-bit.
Whether the host bridge uses internal translations or not to map the 
non-prefetchable resources to 64-bit space, the size needs to be 
programmed in the host bridge's 'Memory Limit Register (Offset 22h)' 
which can represent sizes only fit into 32-bits.
Host bridges having the ability to map 64-bit address spaces gives 
flexibility to utilize the vast 64-bit space for the (restrictive) 
non-prefetchable memory (i.e. mapping non-prefetchable BARs of endpoints 
to the 64-bit space in CPU's view) and get it translated internally and 
put a 32-bit address on the PCIe bus finally.

- Vidya Sagar
> 
> Relax the condition to only warn when the resource size requires >
> 32-bits and doesn't allow mapping to 64-bit addresses.
> 
> Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com
> Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
> Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
> Cc: Vidya Sagar <vidyas@nvidia.com>
> ---
>   drivers/pci/of.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index 1e45186a5715..38fe2589beb0 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -581,7 +581,8 @@ static int pci_parse_request_of_pci_ranges(struct device *dev,
>                          res_valid |= !(res->flags & IORESOURCE_PREFETCH);
> 
>                          if (!(res->flags & IORESOURCE_PREFETCH))
> -                               if (upper_32_bits(resource_size(res)))
> +                               if (!(res->flags & IORESOURCE_MEM_64) &&
> +                                   upper_32_bits(resource_size(res)))
>                                          dev_warn(dev, "Memory resource size exceeds max for 32 bits\n");
> 
>                          break;
> --
> 2.30.2
> 

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