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From: Punit Agrawal <punitagrawal@gmail.com>
To: helgaas@kernel.org, robh+dt@kernel.org
Cc: Punit Agrawal <punitagrawal@gmail.com>,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	alexandru.elisei@arm.com, wqu@suse.com, robin.murphy@arm.com,
	pgwipeout@gmail.com, ardb@kernel.org, briannorris@chromium.org,
	shawn.lin@rock-chips.com, Bjorn Helgaas <bhelgaas@google.com>
Subject: [PATCH v3 1/4] PCI: of: Clear 64-bit flag for non-prefetchable memory below 4GB
Date: Mon,  7 Jun 2021 20:28:53 +0900	[thread overview]
Message-ID: <20210607112856.3499682-2-punitagrawal@gmail.com> (raw)
In-Reply-To: <20210607112856.3499682-1-punitagrawal@gmail.com>

Some host bridges advertise non-prefetchable memory windows that are
entirely located below 4GB but are marked as 64-bit address memory.

Since commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource
flags for 64-bit memory addresses"), the OF PCI range parser takes a
stricter view and treats 64-bit address ranges as advertised while
before such ranges were treated as 32-bit.

A PCI root port modelled as a PCI-to-PCI bridge cannot forward 64-bit
non-prefetchable memory ranges. As a result, the change in behaviour
due to the commit causes failure to allocate 32-bit BAR from a 64-bit
non-prefetchable window.

In order to not break platforms where non-prefetchable memory ranges
lie entirely below 4GB, clear the 64-bit flag.

Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com
Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rob Herring <robh+dt@kernel.org>
---
 drivers/pci/of.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 85dcb7097da4..1e45186a5715 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -353,6 +353,14 @@ static int devm_of_pci_get_host_bridge_resources(struct device *dev,
 				dev_warn(dev, "More than one I/O resource converted for %pOF. CPU base address for old range lost!\n",
 					 dev_node);
 			*io_base = range.cpu_addr;
+		} else if (resource_type(res) == IORESOURCE_MEM) {
+			if (!(res->flags & IORESOURCE_PREFETCH)) {
+				if (res->flags & IORESOURCE_MEM_64)
+					if (!upper_32_bits(range.pci_addr + range.size - 1)) {
+						dev_warn(dev, "Clearing 64-bit flag for non-prefetchable memory below 4GB\n");
+						res->flags &= ~IORESOURCE_MEM_64;
+					}
+			}
 		}
 
 		pci_add_resource_offset(resources, res,	res->start - range.pci_addr);
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Punit Agrawal <punitagrawal@gmail.com>
To: helgaas@kernel.org, robh+dt@kernel.org
Cc: Punit Agrawal <punitagrawal@gmail.com>,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	alexandru.elisei@arm.com, wqu@suse.com, robin.murphy@arm.com,
	pgwipeout@gmail.com, ardb@kernel.org, briannorris@chromium.org,
	shawn.lin@rock-chips.com, Bjorn Helgaas <bhelgaas@google.com>
Subject: [PATCH v3 1/4] PCI: of: Clear 64-bit flag for non-prefetchable memory below 4GB
Date: Mon,  7 Jun 2021 20:28:53 +0900	[thread overview]
Message-ID: <20210607112856.3499682-2-punitagrawal@gmail.com> (raw)
In-Reply-To: <20210607112856.3499682-1-punitagrawal@gmail.com>

Some host bridges advertise non-prefetchable memory windows that are
entirely located below 4GB but are marked as 64-bit address memory.

Since commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource
flags for 64-bit memory addresses"), the OF PCI range parser takes a
stricter view and treats 64-bit address ranges as advertised while
before such ranges were treated as 32-bit.

A PCI root port modelled as a PCI-to-PCI bridge cannot forward 64-bit
non-prefetchable memory ranges. As a result, the change in behaviour
due to the commit causes failure to allocate 32-bit BAR from a 64-bit
non-prefetchable window.

In order to not break platforms where non-prefetchable memory ranges
lie entirely below 4GB, clear the 64-bit flag.

Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com
Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rob Herring <robh+dt@kernel.org>
---
 drivers/pci/of.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 85dcb7097da4..1e45186a5715 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -353,6 +353,14 @@ static int devm_of_pci_get_host_bridge_resources(struct device *dev,
 				dev_warn(dev, "More than one I/O resource converted for %pOF. CPU base address for old range lost!\n",
 					 dev_node);
 			*io_base = range.cpu_addr;
+		} else if (resource_type(res) == IORESOURCE_MEM) {
+			if (!(res->flags & IORESOURCE_PREFETCH)) {
+				if (res->flags & IORESOURCE_MEM_64)
+					if (!upper_32_bits(range.pci_addr + range.size - 1)) {
+						dev_warn(dev, "Clearing 64-bit flag for non-prefetchable memory below 4GB\n");
+						res->flags &= ~IORESOURCE_MEM_64;
+					}
+			}
 		}
 
 		pci_add_resource_offset(resources, res,	res->start - range.pci_addr);
-- 
2.30.2


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Punit Agrawal <punitagrawal@gmail.com>
To: helgaas@kernel.org, robh+dt@kernel.org
Cc: Punit Agrawal <punitagrawal@gmail.com>,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	alexandru.elisei@arm.com, wqu@suse.com, robin.murphy@arm.com,
	pgwipeout@gmail.com, ardb@kernel.org, briannorris@chromium.org,
	shawn.lin@rock-chips.com, Bjorn Helgaas <bhelgaas@google.com>
Subject: [PATCH v3 1/4] PCI: of: Clear 64-bit flag for non-prefetchable memory below 4GB
Date: Mon,  7 Jun 2021 20:28:53 +0900	[thread overview]
Message-ID: <20210607112856.3499682-2-punitagrawal@gmail.com> (raw)
In-Reply-To: <20210607112856.3499682-1-punitagrawal@gmail.com>

Some host bridges advertise non-prefetchable memory windows that are
entirely located below 4GB but are marked as 64-bit address memory.

Since commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource
flags for 64-bit memory addresses"), the OF PCI range parser takes a
stricter view and treats 64-bit address ranges as advertised while
before such ranges were treated as 32-bit.

A PCI root port modelled as a PCI-to-PCI bridge cannot forward 64-bit
non-prefetchable memory ranges. As a result, the change in behaviour
due to the commit causes failure to allocate 32-bit BAR from a 64-bit
non-prefetchable window.

In order to not break platforms where non-prefetchable memory ranges
lie entirely below 4GB, clear the 64-bit flag.

Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com
Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rob Herring <robh+dt@kernel.org>
---
 drivers/pci/of.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 85dcb7097da4..1e45186a5715 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -353,6 +353,14 @@ static int devm_of_pci_get_host_bridge_resources(struct device *dev,
 				dev_warn(dev, "More than one I/O resource converted for %pOF. CPU base address for old range lost!\n",
 					 dev_node);
 			*io_base = range.cpu_addr;
+		} else if (resource_type(res) == IORESOURCE_MEM) {
+			if (!(res->flags & IORESOURCE_PREFETCH)) {
+				if (res->flags & IORESOURCE_MEM_64)
+					if (!upper_32_bits(range.pci_addr + range.size - 1)) {
+						dev_warn(dev, "Clearing 64-bit flag for non-prefetchable memory below 4GB\n");
+						res->flags &= ~IORESOURCE_MEM_64;
+					}
+			}
 		}
 
 		pci_add_resource_offset(resources, res,	res->start - range.pci_addr);
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-06-07 11:30 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-07 11:28 [PATCH v3 0/4] PCI: of: Improvements to handle 64-bit attribute for non-prefetchable ranges Punit Agrawal
2021-06-07 11:28 ` Punit Agrawal
2021-06-07 11:28 ` Punit Agrawal
2021-06-07 11:28 ` Punit Agrawal [this message]
2021-06-07 11:28   ` [PATCH v3 1/4] PCI: of: Clear 64-bit flag for non-prefetchable memory below 4GB Punit Agrawal
2021-06-07 11:28   ` Punit Agrawal
2021-06-10  0:22   ` Bjorn Helgaas
2021-06-10  0:22     ` Bjorn Helgaas
2021-06-10  0:22     ` Bjorn Helgaas
2021-06-10 13:34     ` Punit Agrawal
2021-06-10 13:34       ` Punit Agrawal
2021-06-10 13:34       ` Punit Agrawal
2021-06-10 18:28       ` Bjorn Helgaas
2021-06-10 18:28         ` Bjorn Helgaas
2021-06-10 18:28         ` Bjorn Helgaas
2021-06-07 11:28 ` [PATCH v3 2/4] PCI: of: Relax the condition for warning about non-prefetchable memory aperture size Punit Agrawal
2021-06-07 11:28   ` Punit Agrawal
2021-06-07 11:28   ` Punit Agrawal
2021-06-08 19:06   ` Vidya Sagar
2021-06-08 19:06     ` Vidya Sagar
2021-06-08 19:06     ` Vidya Sagar
2021-06-10  4:04     ` Bjorn Helgaas
2021-06-10  4:04       ` Bjorn Helgaas
2021-06-10  4:04       ` Bjorn Helgaas
2021-06-10 14:11       ` Punit Agrawal
2021-06-10 14:11         ` Punit Agrawal
2021-06-10 14:11         ` Punit Agrawal
2021-06-10 19:58         ` Bjorn Helgaas
2021-06-10 19:58           ` Bjorn Helgaas
2021-06-10 19:58           ` Bjorn Helgaas
2021-06-07 11:28 ` [PATCH v3 3/4] PCI: of: Refactor the check for non-prefetchable 32-bit window Punit Agrawal
2021-06-07 11:28   ` Punit Agrawal
2021-06-07 11:28   ` Punit Agrawal
2021-06-07 11:28 ` [PATCH v3 4/4] arm64: dts: rockchip: Update PCI host bridge window to 32-bit address memory Punit Agrawal
2021-06-07 11:28   ` Punit Agrawal
2021-06-07 11:28   ` Punit Agrawal
2021-06-10 21:50   ` Heiko Stübner
2021-06-10 21:50     ` Heiko Stübner
2021-06-10 21:50     ` Heiko Stübner
2021-06-11 14:38     ` Punit Agrawal
2021-06-11 14:38       ` Punit Agrawal
2021-06-11 14:38       ` Punit Agrawal
2021-06-15 21:29     ` Rob Herring
2021-06-15 21:29       ` Rob Herring
2021-06-15 21:29       ` Rob Herring
2021-06-15 21:49       ` Heiko Stübner
2021-06-15 21:49         ` Heiko Stübner
2021-06-15 21:49         ` Heiko Stübner
2021-06-16 13:00         ` Punit Agrawal
2021-06-16 13:00           ` Punit Agrawal
2021-06-16 13:00           ` Punit Agrawal
2021-06-09 16:08 ` [PATCH v3 0/4] PCI: of: Improvements to handle 64-bit attribute for non-prefetchable ranges Marc Zyngier
2021-06-09 16:08   ` Marc Zyngier
2021-06-09 16:08   ` Marc Zyngier
2021-06-10 14:17   ` Punit Agrawal
2021-06-10 14:17     ` Punit Agrawal
2021-06-10 14:17     ` Punit Agrawal
2021-06-10  9:05 ` Anand Moon
2021-06-10  9:05   ` Anand Moon
2021-06-10  9:05   ` Anand Moon
2021-06-10 14:25   ` Punit Agrawal
2021-06-10 14:25     ` Punit Agrawal
2021-06-10 14:25     ` Punit Agrawal
2021-06-10 18:36     ` Anand Moon
2021-06-10 18:36       ` Anand Moon
2021-06-10 18:36       ` Anand Moon
2021-06-11 22:15 ` (subset) " Heiko Stuebner
2021-06-11 22:15   ` Heiko Stuebner
2021-06-11 22:15   ` Heiko Stuebner

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