From: Anup Patel <anup@brainfault.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup.patel@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
Date: Mon, 12 Jul 2021 11:08:59 +0530 [thread overview]
Message-ID: <CAAhSdy2q7S08eF8NfqvEeFORkrGDaZsDJftCTaq7c9zi7WU2SQ@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmV1L7sL+9=3=onkXZoR0FYpV93gKCVxFJ5O5-Jw36PQgA@mail.gmail.com>
On Mon, Jun 14, 2021 at 5:52 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sun, Jun 13, 2021 at 12:14 AM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > We extend virt machine to emulate ACLINT devices only when "aclint=on"
> > parameter is passed along with machine name in QEMU command-line.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > hw/riscv/virt.c | 110 +++++++++++++++++++++++++++++++++++++++-
> > include/hw/riscv/virt.h | 2 +
> > 2 files changed, 111 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index 977d699753..a35f66af13 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -50,6 +50,7 @@ static const MemMapEntry virt_memmap[] = {
> > [VIRT_TEST] = { 0x100000, 0x1000 },
> > [VIRT_RTC] = { 0x101000, 0x1000 },
> > [VIRT_CLINT] = { 0x2000000, 0x10000 },
> > + [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
>
> How about we reuse the same register space to support both CLINT and
> ACLINT? This saves some register space for future extension.
The intention of placing ACLINT SSWI separate from ACLINT MTIMER and
MSWI is to minimize PMP region usage.
When we have multiple sockets, each socket will have it's own set of
ACLINT devices so we deliberately keep ACLINT MTIMER and MSWI
devices of all sockets next to each other so that we need just 1-2 PMP
regions to cover all M-level ACLINT devices.
In general, RISC-V platform vendors will have to carefully design
memory layout of M-level devices so that M-mode runtime firmware
needs fewer PMP regions. The spare PMP regions can be used by
M-mode runtime firmware to partition the system into domains and
implement TEE.
>
> > [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
> > [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
> > [VIRT_UART0] = { 0x10000000, 0x100 },
> > @@ -279,6 +280,78 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
> > g_free(clint_cells);
> > }
> >
> > +static void create_fdt_socket_aclint(RISCVVirtState *s,
> > + const MemMapEntry *memmap, int socket,
> > + uint32_t *intc_phandles)
> > +{
> > + int cpu;
> > + char *name;
> > + unsigned long addr;
> > + uint32_t aclint_cells_size;
> > + uint32_t *aclint_mswi_cells;
> > + uint32_t *aclint_sswi_cells;
> > + uint32_t *aclint_mtimer_cells;
> > + MachineState *mc = MACHINE(s);
> > +
> > + aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
> > + aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
> > + aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
> > +
> > + for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
> > + aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
> > + aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
> > + aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
> > + aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
> > + aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
> > + aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
> > + }
> > + aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
> > +
> > + addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
> > + name = g_strdup_printf("/soc/mswi@%lx", addr);
> > + qemu_fdt_add_subnode(mc->fdt, name);
> > + qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi");
> > + qemu_fdt_setprop_cells(mc->fdt, name, "reg",
> > + 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
> > + aclint_mswi_cells, aclint_cells_size);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
> > + qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
> > + riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
> > + g_free(name);
> > +
> > + addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
> > + (memmap[VIRT_CLINT].size * socket);
> > + name = g_strdup_printf("/soc/mtimer@%lx", addr);
> > + qemu_fdt_add_subnode(mc->fdt, name);
> > + qemu_fdt_setprop_string(mc->fdt, name, "compatible",
> > + "riscv,aclint-mtimer");
> > + qemu_fdt_setprop_cells(mc->fdt, name, "reg",
> > + 0x0, addr, 0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
> > + aclint_mtimer_cells, aclint_cells_size);
> > + riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
> > + g_free(name);
> > +
> > + addr = memmap[VIRT_ACLINT_SSWI].base +
> > + (memmap[VIRT_ACLINT_SSWI].size * socket);
> > + name = g_strdup_printf("/soc/sswi@%lx", addr);
> > + qemu_fdt_add_subnode(mc->fdt, name);
> > + qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi");
> > + qemu_fdt_setprop_cells(mc->fdt, name, "reg",
> > + 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
> > + aclint_sswi_cells, aclint_cells_size);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
> > + qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
> > + riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
> > + g_free(name);
> > +
> > + g_free(aclint_mswi_cells);
> > + g_free(aclint_mtimer_cells);
> > + g_free(aclint_sswi_cells);
> > +}
> > +
> > static void create_fdt_socket_plic(RISCVVirtState *s,
> > const MemMapEntry *memmap, int socket,
> > uint32_t *phandle, uint32_t *intc_phandles,
> > @@ -352,7 +425,11 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
> >
> > create_fdt_socket_memory(s, memmap, socket);
> >
> > - create_fdt_socket_clint(s, memmap, socket, intc_phandles);
> > + if (s->have_aclint) {
> > + create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
> > + } else {
> > + create_fdt_socket_clint(s, memmap, socket, intc_phandles);
> > + }
> >
> > create_fdt_socket_plic(s, memmap, socket, phandle,
> > intc_phandles, xplic_phandles);
> > @@ -722,6 +799,15 @@ static void virt_machine_init(MachineState *machine)
> > RISCV_ACLINT_MTIMER_SIZE, base_hartid, hart_count,
> > RISCV_ACLINT_TIMEBASE_FREQ, true);
> >
> > + /* Per-socket ACLINT SSWI */
> > + if (s->have_aclint) {
> > + riscv_aclint_swi_create(
> > + memmap[VIRT_ACLINT_SSWI].base +
> > + i * memmap[VIRT_ACLINT_SSWI].size,
> > + memmap[VIRT_ACLINT_SSWI].size,
> > + base_hartid, hart_count, true);
> > + }
> > +
> > /* Per-socket PLIC hart topology configuration string */
> > plic_hart_config_len =
> > (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
> > @@ -898,6 +984,22 @@ static void virt_machine_instance_init(Object *obj)
> > {
> > }
> >
> > +static bool virt_get_aclint(Object *obj, Error **errp)
> > +{
> > + MachineState *ms = MACHINE(obj);
> > + RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
> > +
> > + return s->have_aclint;
> > +}
> > +
> > +static void virt_set_aclint(Object *obj, bool value, Error **errp)
> > +{
> > + MachineState *ms = MACHINE(obj);
> > + RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
> > +
> > + s->have_aclint = value;
> > +}
> > +
> > static void virt_machine_class_init(ObjectClass *oc, void *data)
> > {
> > MachineClass *mc = MACHINE_CLASS(oc);
> > @@ -913,6 +1015,12 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
> > mc->numa_mem_supported = true;
> >
> > machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
> > +
> > + object_class_property_add_bool(oc, "aclint", virt_get_aclint,
> > + virt_set_aclint);
> > + object_class_property_set_description(oc, "aclint",
> > + "Set on/off to enable/disable "
> > + "emulating ACLINT devices");
> > }
> >
> > static const TypeInfo virt_machine_typeinfo = {
> > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> > index 349fee1f89..d9105c1886 100644
> > --- a/include/hw/riscv/virt.h
> > +++ b/include/hw/riscv/virt.h
> > @@ -43,6 +43,7 @@ struct RISCVVirtState {
> > FWCfgState *fw_cfg;
> >
> > int fdt_size;
> > + bool have_aclint;
> > };
> >
> > enum {
> > @@ -51,6 +52,7 @@ enum {
> > VIRT_TEST,
> > VIRT_RTC,
> > VIRT_CLINT,
> > + VIRT_ACLINT_SSWI,
> > VIRT_PLIC,
> > VIRT_UART0,
> > VIRT_VIRTIO,
>
> Regards,
> Bin
Regards,
Anup
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Anup Patel <anup.patel@wdc.com>,
Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Atish Patra <atish.patra@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
Date: Mon, 12 Jul 2021 11:08:59 +0530 [thread overview]
Message-ID: <CAAhSdy2q7S08eF8NfqvEeFORkrGDaZsDJftCTaq7c9zi7WU2SQ@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmV1L7sL+9=3=onkXZoR0FYpV93gKCVxFJ5O5-Jw36PQgA@mail.gmail.com>
On Mon, Jun 14, 2021 at 5:52 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sun, Jun 13, 2021 at 12:14 AM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > We extend virt machine to emulate ACLINT devices only when "aclint=on"
> > parameter is passed along with machine name in QEMU command-line.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > hw/riscv/virt.c | 110 +++++++++++++++++++++++++++++++++++++++-
> > include/hw/riscv/virt.h | 2 +
> > 2 files changed, 111 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index 977d699753..a35f66af13 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -50,6 +50,7 @@ static const MemMapEntry virt_memmap[] = {
> > [VIRT_TEST] = { 0x100000, 0x1000 },
> > [VIRT_RTC] = { 0x101000, 0x1000 },
> > [VIRT_CLINT] = { 0x2000000, 0x10000 },
> > + [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
>
> How about we reuse the same register space to support both CLINT and
> ACLINT? This saves some register space for future extension.
The intention of placing ACLINT SSWI separate from ACLINT MTIMER and
MSWI is to minimize PMP region usage.
When we have multiple sockets, each socket will have it's own set of
ACLINT devices so we deliberately keep ACLINT MTIMER and MSWI
devices of all sockets next to each other so that we need just 1-2 PMP
regions to cover all M-level ACLINT devices.
In general, RISC-V platform vendors will have to carefully design
memory layout of M-level devices so that M-mode runtime firmware
needs fewer PMP regions. The spare PMP regions can be used by
M-mode runtime firmware to partition the system into domains and
implement TEE.
>
> > [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
> > [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
> > [VIRT_UART0] = { 0x10000000, 0x100 },
> > @@ -279,6 +280,78 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
> > g_free(clint_cells);
> > }
> >
> > +static void create_fdt_socket_aclint(RISCVVirtState *s,
> > + const MemMapEntry *memmap, int socket,
> > + uint32_t *intc_phandles)
> > +{
> > + int cpu;
> > + char *name;
> > + unsigned long addr;
> > + uint32_t aclint_cells_size;
> > + uint32_t *aclint_mswi_cells;
> > + uint32_t *aclint_sswi_cells;
> > + uint32_t *aclint_mtimer_cells;
> > + MachineState *mc = MACHINE(s);
> > +
> > + aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
> > + aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
> > + aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
> > +
> > + for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
> > + aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
> > + aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
> > + aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
> > + aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
> > + aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
> > + aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
> > + }
> > + aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
> > +
> > + addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
> > + name = g_strdup_printf("/soc/mswi@%lx", addr);
> > + qemu_fdt_add_subnode(mc->fdt, name);
> > + qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi");
> > + qemu_fdt_setprop_cells(mc->fdt, name, "reg",
> > + 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
> > + aclint_mswi_cells, aclint_cells_size);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
> > + qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
> > + riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
> > + g_free(name);
> > +
> > + addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
> > + (memmap[VIRT_CLINT].size * socket);
> > + name = g_strdup_printf("/soc/mtimer@%lx", addr);
> > + qemu_fdt_add_subnode(mc->fdt, name);
> > + qemu_fdt_setprop_string(mc->fdt, name, "compatible",
> > + "riscv,aclint-mtimer");
> > + qemu_fdt_setprop_cells(mc->fdt, name, "reg",
> > + 0x0, addr, 0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
> > + aclint_mtimer_cells, aclint_cells_size);
> > + riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
> > + g_free(name);
> > +
> > + addr = memmap[VIRT_ACLINT_SSWI].base +
> > + (memmap[VIRT_ACLINT_SSWI].size * socket);
> > + name = g_strdup_printf("/soc/sswi@%lx", addr);
> > + qemu_fdt_add_subnode(mc->fdt, name);
> > + qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi");
> > + qemu_fdt_setprop_cells(mc->fdt, name, "reg",
> > + 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
> > + aclint_sswi_cells, aclint_cells_size);
> > + qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
> > + qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
> > + riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
> > + g_free(name);
> > +
> > + g_free(aclint_mswi_cells);
> > + g_free(aclint_mtimer_cells);
> > + g_free(aclint_sswi_cells);
> > +}
> > +
> > static void create_fdt_socket_plic(RISCVVirtState *s,
> > const MemMapEntry *memmap, int socket,
> > uint32_t *phandle, uint32_t *intc_phandles,
> > @@ -352,7 +425,11 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
> >
> > create_fdt_socket_memory(s, memmap, socket);
> >
> > - create_fdt_socket_clint(s, memmap, socket, intc_phandles);
> > + if (s->have_aclint) {
> > + create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
> > + } else {
> > + create_fdt_socket_clint(s, memmap, socket, intc_phandles);
> > + }
> >
> > create_fdt_socket_plic(s, memmap, socket, phandle,
> > intc_phandles, xplic_phandles);
> > @@ -722,6 +799,15 @@ static void virt_machine_init(MachineState *machine)
> > RISCV_ACLINT_MTIMER_SIZE, base_hartid, hart_count,
> > RISCV_ACLINT_TIMEBASE_FREQ, true);
> >
> > + /* Per-socket ACLINT SSWI */
> > + if (s->have_aclint) {
> > + riscv_aclint_swi_create(
> > + memmap[VIRT_ACLINT_SSWI].base +
> > + i * memmap[VIRT_ACLINT_SSWI].size,
> > + memmap[VIRT_ACLINT_SSWI].size,
> > + base_hartid, hart_count, true);
> > + }
> > +
> > /* Per-socket PLIC hart topology configuration string */
> > plic_hart_config_len =
> > (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
> > @@ -898,6 +984,22 @@ static void virt_machine_instance_init(Object *obj)
> > {
> > }
> >
> > +static bool virt_get_aclint(Object *obj, Error **errp)
> > +{
> > + MachineState *ms = MACHINE(obj);
> > + RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
> > +
> > + return s->have_aclint;
> > +}
> > +
> > +static void virt_set_aclint(Object *obj, bool value, Error **errp)
> > +{
> > + MachineState *ms = MACHINE(obj);
> > + RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
> > +
> > + s->have_aclint = value;
> > +}
> > +
> > static void virt_machine_class_init(ObjectClass *oc, void *data)
> > {
> > MachineClass *mc = MACHINE_CLASS(oc);
> > @@ -913,6 +1015,12 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
> > mc->numa_mem_supported = true;
> >
> > machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
> > +
> > + object_class_property_add_bool(oc, "aclint", virt_get_aclint,
> > + virt_set_aclint);
> > + object_class_property_set_description(oc, "aclint",
> > + "Set on/off to enable/disable "
> > + "emulating ACLINT devices");
> > }
> >
> > static const TypeInfo virt_machine_typeinfo = {
> > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> > index 349fee1f89..d9105c1886 100644
> > --- a/include/hw/riscv/virt.h
> > +++ b/include/hw/riscv/virt.h
> > @@ -43,6 +43,7 @@ struct RISCVVirtState {
> > FWCfgState *fw_cfg;
> >
> > int fdt_size;
> > + bool have_aclint;
> > };
> >
> > enum {
> > @@ -51,6 +52,7 @@ enum {
> > VIRT_TEST,
> > VIRT_RTC,
> > VIRT_CLINT,
> > + VIRT_ACLINT_SSWI,
> > VIRT_PLIC,
> > VIRT_UART0,
> > VIRT_VIRTIO,
>
> Regards,
> Bin
Regards,
Anup
next prev parent reply other threads:[~2021-07-12 5:41 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-12 16:06 [PATCH v1 0/3] RISC-V ACLINT Support Anup Patel
2021-06-12 16:06 ` Anup Patel
2021-06-12 16:06 ` [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
2021-06-12 16:06 ` Anup Patel
2021-06-14 12:22 ` Bin Meng
2021-06-14 12:22 ` Bin Meng
2021-07-12 5:00 ` Anup Patel
2021-07-12 5:00 ` Anup Patel
2021-06-18 6:50 ` Alistair Francis
2021-06-18 6:50 ` Alistair Francis
2021-07-12 5:32 ` Anup Patel
2021-07-12 5:32 ` Anup Patel
2021-06-12 16:06 ` [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation Anup Patel
2021-06-12 16:06 ` Anup Patel
2021-06-14 12:22 ` Bin Meng
2021-06-14 12:22 ` Bin Meng
2021-07-12 5:40 ` Anup Patel
2021-07-12 5:40 ` Anup Patel
2021-06-12 16:06 ` [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel
2021-06-12 16:06 ` Anup Patel
2021-06-14 12:22 ` Bin Meng
2021-06-14 12:22 ` Bin Meng
2021-07-12 5:38 ` Anup Patel [this message]
2021-07-12 5:38 ` Anup Patel
2021-07-12 6:15 ` Bin Meng
2021-07-12 6:15 ` Bin Meng
2021-07-12 10:53 ` Anup Patel
2021-07-12 10:53 ` Anup Patel
2021-07-12 13:11 ` Bin Meng
2021-07-12 13:11 ` Bin Meng
2021-07-12 15:02 ` Anup Patel
2021-07-12 15:02 ` Anup Patel
2021-07-12 23:05 ` Bin Meng
2021-07-12 23:05 ` Bin Meng
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