From: Anup Patel <anup@brainfault.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup.patel@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
Date: Mon, 12 Jul 2021 16:23:59 +0530 [thread overview]
Message-ID: <CAAhSdy1QW+sQi0L+NfCSfL6k4ZQaU9sqt=ZdDQ=ZK8ygykZnxg@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmW9XEk0rZivzQTMhFwL4Egjh0jR9HxEnwJMSOyBntiQig@mail.gmail.com>
On Mon, Jul 12, 2021 at 11:45 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Jul 12, 2021 at 1:39 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Mon, Jun 14, 2021 at 5:52 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > On Sun, Jun 13, 2021 at 12:14 AM Anup Patel <anup.patel@wdc.com> wrote:
> > > >
> > > > We extend virt machine to emulate ACLINT devices only when "aclint=on"
> > > > parameter is passed along with machine name in QEMU command-line.
> > > >
> > > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > > ---
> > > > hw/riscv/virt.c | 110 +++++++++++++++++++++++++++++++++++++++-
> > > > include/hw/riscv/virt.h | 2 +
> > > > 2 files changed, 111 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > > > index 977d699753..a35f66af13 100644
> > > > --- a/hw/riscv/virt.c
> > > > +++ b/hw/riscv/virt.c
> > > > @@ -50,6 +50,7 @@ static const MemMapEntry virt_memmap[] = {
> > > > [VIRT_TEST] = { 0x100000, 0x1000 },
> > > > [VIRT_RTC] = { 0x101000, 0x1000 },
> > > > [VIRT_CLINT] = { 0x2000000, 0x10000 },
> > > > + [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
> > >
> > > How about we reuse the same register space to support both CLINT and
> > > ACLINT? This saves some register space for future extension.
> >
> > The intention of placing ACLINT SSWI separate from ACLINT MTIMER and
> > MSWI is to minimize PMP region usage.
>
> Okay, so this leaves spaces for 240 ACLINT MTIMER and MSWI devices in
> total, if we put ACLINT SSWI at 0x2F00000, and we still have spaces
> for 64 ACLINT SSWI devices. Is this enough?
We just need one instance of MTIMER, MSWI, and SSWI per-socket.
Current limit of max sockets in RISC-V virt machine is 8. We will be
reducing this to 4 due space required by IMSICs. This means no matter
what 8 instances of each MTIMER, MSWI, and SSWI is the max we
can go for RISC-V virt machine. This limits are due to the fact that
we want to fit devices in first 2GB space.
Regards,
Anup
>
> >
> > When we have multiple sockets, each socket will have it's own set of
> > ACLINT devices so we deliberately keep ACLINT MTIMER and MSWI
> > devices of all sockets next to each other so that we need just 1-2 PMP
> > regions to cover all M-level ACLINT devices.
> >
> > In general, RISC-V platform vendors will have to carefully design
> > memory layout of M-level devices so that M-mode runtime firmware
> > needs fewer PMP regions. The spare PMP regions can be used by
> > M-mode runtime firmware to partition the system into domains and
> > implement TEE.
> >
> > >
> > > > [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
> > > > [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
> > > > [VIRT_UART0] = { 0x10000000, 0x100 },
> > > > @@ -279,6 +280,78 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
> > > > g_free(clint_cells);
> > > > }
>
> Regards,
> Bin
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Anup Patel <anup.patel@wdc.com>,
Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Atish Patra <atish.patra@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
Date: Mon, 12 Jul 2021 16:23:59 +0530 [thread overview]
Message-ID: <CAAhSdy1QW+sQi0L+NfCSfL6k4ZQaU9sqt=ZdDQ=ZK8ygykZnxg@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmW9XEk0rZivzQTMhFwL4Egjh0jR9HxEnwJMSOyBntiQig@mail.gmail.com>
On Mon, Jul 12, 2021 at 11:45 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Jul 12, 2021 at 1:39 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Mon, Jun 14, 2021 at 5:52 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > On Sun, Jun 13, 2021 at 12:14 AM Anup Patel <anup.patel@wdc.com> wrote:
> > > >
> > > > We extend virt machine to emulate ACLINT devices only when "aclint=on"
> > > > parameter is passed along with machine name in QEMU command-line.
> > > >
> > > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > > ---
> > > > hw/riscv/virt.c | 110 +++++++++++++++++++++++++++++++++++++++-
> > > > include/hw/riscv/virt.h | 2 +
> > > > 2 files changed, 111 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > > > index 977d699753..a35f66af13 100644
> > > > --- a/hw/riscv/virt.c
> > > > +++ b/hw/riscv/virt.c
> > > > @@ -50,6 +50,7 @@ static const MemMapEntry virt_memmap[] = {
> > > > [VIRT_TEST] = { 0x100000, 0x1000 },
> > > > [VIRT_RTC] = { 0x101000, 0x1000 },
> > > > [VIRT_CLINT] = { 0x2000000, 0x10000 },
> > > > + [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
> > >
> > > How about we reuse the same register space to support both CLINT and
> > > ACLINT? This saves some register space for future extension.
> >
> > The intention of placing ACLINT SSWI separate from ACLINT MTIMER and
> > MSWI is to minimize PMP region usage.
>
> Okay, so this leaves spaces for 240 ACLINT MTIMER and MSWI devices in
> total, if we put ACLINT SSWI at 0x2F00000, and we still have spaces
> for 64 ACLINT SSWI devices. Is this enough?
We just need one instance of MTIMER, MSWI, and SSWI per-socket.
Current limit of max sockets in RISC-V virt machine is 8. We will be
reducing this to 4 due space required by IMSICs. This means no matter
what 8 instances of each MTIMER, MSWI, and SSWI is the max we
can go for RISC-V virt machine. This limits are due to the fact that
we want to fit devices in first 2GB space.
Regards,
Anup
>
> >
> > When we have multiple sockets, each socket will have it's own set of
> > ACLINT devices so we deliberately keep ACLINT MTIMER and MSWI
> > devices of all sockets next to each other so that we need just 1-2 PMP
> > regions to cover all M-level ACLINT devices.
> >
> > In general, RISC-V platform vendors will have to carefully design
> > memory layout of M-level devices so that M-mode runtime firmware
> > needs fewer PMP regions. The spare PMP regions can be used by
> > M-mode runtime firmware to partition the system into domains and
> > implement TEE.
> >
> > >
> > > > [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
> > > > [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
> > > > [VIRT_UART0] = { 0x10000000, 0x100 },
> > > > @@ -279,6 +280,78 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
> > > > g_free(clint_cells);
> > > > }
>
> Regards,
> Bin
next prev parent reply other threads:[~2021-07-12 10:55 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-12 16:06 [PATCH v1 0/3] RISC-V ACLINT Support Anup Patel
2021-06-12 16:06 ` Anup Patel
2021-06-12 16:06 ` [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
2021-06-12 16:06 ` Anup Patel
2021-06-14 12:22 ` Bin Meng
2021-06-14 12:22 ` Bin Meng
2021-07-12 5:00 ` Anup Patel
2021-07-12 5:00 ` Anup Patel
2021-06-18 6:50 ` Alistair Francis
2021-06-18 6:50 ` Alistair Francis
2021-07-12 5:32 ` Anup Patel
2021-07-12 5:32 ` Anup Patel
2021-06-12 16:06 ` [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation Anup Patel
2021-06-12 16:06 ` Anup Patel
2021-06-14 12:22 ` Bin Meng
2021-06-14 12:22 ` Bin Meng
2021-07-12 5:40 ` Anup Patel
2021-07-12 5:40 ` Anup Patel
2021-06-12 16:06 ` [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel
2021-06-12 16:06 ` Anup Patel
2021-06-14 12:22 ` Bin Meng
2021-06-14 12:22 ` Bin Meng
2021-07-12 5:38 ` Anup Patel
2021-07-12 5:38 ` Anup Patel
2021-07-12 6:15 ` Bin Meng
2021-07-12 6:15 ` Bin Meng
2021-07-12 10:53 ` Anup Patel [this message]
2021-07-12 10:53 ` Anup Patel
2021-07-12 13:11 ` Bin Meng
2021-07-12 13:11 ` Bin Meng
2021-07-12 15:02 ` Anup Patel
2021-07-12 15:02 ` Anup Patel
2021-07-12 23:05 ` Bin Meng
2021-07-12 23:05 ` Bin Meng
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