messages from 2021-06-16 09:16:13 to 2021-07-12 05:41:25 UTC [more...]
[PATCH v1 0/3] RISC-V ACLINT Support
2021-07-12 5:40 UTC (12+ messages)
` [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
` [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation
` [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
[PATCH v2 0/3] Updates to the OpenTitan machine
2021-07-12 5:13 UTC (6+ messages)
` [PATCH v2 1/3] char: ibex_uart: Update the register layout
` [PATCH v2 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
` [PATCH v2 3/3] hw/riscv: opentitan: Add the flash alias
[PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
2021-07-12 4:49 UTC (16+ messages)
` [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU "
` [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use "
` [PATCH v1 4/5] hw/intc: sifive_plic: "
` [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer "
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-07-10 15:04 UTC (61+ messages)
` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode
` [RFC PATCH 03/11] hw/intc: Add CLIC device
` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode
` [RFC PATCH 05/11] target/riscv: Update CSR xip "
` [RFC PATCH 06/11] target/riscv: Update CSR xtvec "
` [RFC PATCH 07/11] target/riscv: Update CSR xtvt "
` [RFC PATCH 08/11] target/riscv: Update CSR xnxti "
` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase "
` [RFC PATCH 10/11] target/riscv: Update interrupt handling "
` [RFC PATCH 11/11] target/riscv: Update interrupt return "
[PATCH 00/17] target/riscv: Use tcg_constant_*
2021-07-09 16:20 UTC (21+ messages)
` [PATCH 01/17] "
` [PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst
` [PATCH 03/17] target/riscv: Use gpr_{src,dst} in shift operations
` [PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations
` [PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi
` [PATCH 06/17] target/riscv: Use gpr_src in branches
` [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store
` [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations
` [PATCH 09/17] target/riscv: Reorg csr instructions
` [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA
` [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB
` [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF
` [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD
` [PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc
` [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu
` [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV
` [PATCH 17/17] target/riscv: Remove gen_get_gpr
[PATCH] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
2021-07-09 4:41 UTC (3+ messages)
[PATCH] hw/riscv: sifive_u: Correct the CLINT timebase frequency
2021-07-09 3:50 UTC (3+ messages)
[PATCH] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
2021-07-09 3:50 UTC (3+ messages)
[PATCH] target/riscv: hardwire bits in hideleg and hedeleg
2021-07-08 4:45 UTC (4+ messages)
[PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
2021-07-07 19:15 UTC (4+ messages)
[PATCH v2 1/5] meson: Introduce target-specific Kconfig
2021-07-07 13:17 UTC
[PATCH v2 32/36] linux-user/riscv: Add vdso and use it for sigreturn
2021-07-06 23:49 UTC
[PATCH v1 1/5] meson: Introduce target-specific Kconfig
2021-07-06 13:52 UTC (6+ messages)
[PATCH v1 0/3] Updates to the OpenTitan machine
2021-07-06 4:49 UTC (8+ messages)
` [PATCH v1 1/3] char: ibex_uart: Update the register layout
` [PATCH v1 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
` [PATCH v1 3/3] hw/riscv: opentitan: Add the flash alias
[PATCH v2] linux-user/elfload: Implement ELF_HWCAP for RISC-V
2021-07-06 3:28 UTC (2+ messages)
[PATCH 1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc
2021-07-05 5:35 UTC (5+ messages)
` [PATCH 2/2] docs/system: riscv: Add documentation for virt machine
[PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines
2021-07-02 7:22 UTC (2+ messages)
[PATCH v3 00/37] target/riscv: support packed extension v0.9.4
2021-07-01 3:06 UTC (43+ messages)
` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters
` [PATCH v3 02/37] target/riscv: Make the vector helper functions public
` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions
` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions
` [PATCH v3 06/37] target/riscv: SIMD 8-bit "
` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions
` [PATCH v3 08/37] target/riscv: SIMD 8-bit "
` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions
` [PATCH v3 10/37] target/riscv: SIMD 8-bit "
` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions
` [PATCH v3 12/37] target/riscv: SIMD 8-bit "
` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions
` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions
` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions
` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 "
` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit "
` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions
` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions
` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions
` [PATCH v3 22/37] target/riscv: 32-bit Multiply "
` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with "
` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions
` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 "
` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions
` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions
` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit "
` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel "
` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions
` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line
[PATCH] target/riscv: pmp: Fix some typos
2021-07-01 1:27 UTC (4+ messages)
[PATCH v2 00/37] target/riscv: support packed extension v0.9.4
2021-06-24 6:05 UTC (4+ messages)
` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
[PATCH v3 0/3] OpenTitan: Add support for the RISC-V timer
2021-06-21 22:39 UTC (6+ messages)
` [PATCH v3 1/3] hw/char/ibex_uart: Make the register layout private
` [PATCH v3 2/3] hw/timer: Initial commit of Ibex Timer
` [PATCH v3 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
[PATCH 18/26] target/riscv: Use translator_use_goto_tb
2021-06-21 22:22 UTC (2+ messages)
[PATCH v16 93/99] meson: Introduce target-specific Kconfig
2021-06-18 16:31 UTC (3+ messages)
[PATCH v5 0/2] QOMify Sifive UART Model
2021-06-18 7:23 UTC (5+ messages)
` [PATCH v5 1/2] hw/char: Consistent function names for sifive_uart
` [PATCH v5 2/2] hw/char: QOMify sifive_uart
[PATCH v2 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer
2021-06-18 7:02 UTC (6+ messages)
` [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
[PATCH] target/riscv: gdbstub: Fix dynamic CSR XML generation
2021-06-18 6:39 UTC (2+ messages)
[PATCH 16/21] linux-user/riscv: Implement setup_sigtramp
2021-06-18 1:29 UTC (3+ messages)
[PATCH v4 0/2] QOMify Sifive UART Model
2021-06-16 9:15 UTC (3+ messages)
` [PATCH v4 2/2] hw/char: QOMify sifive_uart
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