From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk
Subject: Re: [PATCH v2 5/7] target/sparc: Fix FMULD8*X16
Date: Mon, 6 May 2024 16:12:04 +0200 [thread overview]
Message-ID: <f846aaed-5d58-4f23-8a89-fbea80e6f13a@linaro.org> (raw)
In-Reply-To: <20240502165528.244004-6-richard.henderson@linaro.org>
On 2/5/24 18:55, Richard Henderson wrote:
> Not only do these instructions have f32 inputs, they also do not
> perform rounding. Since these are relatively simple, implement
> them properly inline.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/sparc/helper.h | 2 --
> target/sparc/translate.c | 48 +++++++++++++++++++++++++++++++++++----
> target/sparc/vis_helper.c | 46 -------------------------------------
> 3 files changed, 44 insertions(+), 52 deletions(-)
> +static void gen_op_fmuld8ulx16(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2)
> +{
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + TCGv_i32 t2 = tcg_temp_new_i32();
> +
> + tcg_gen_ext8u_i32(t0, src1);
> + tcg_gen_ext16s_i32(t1, src2);
> + tcg_gen_mul_i32(t0, t0, t1);
> +
> + tcg_gen_extract_i32(t1, src1, 16, 8);
> + tcg_gen_sextract_i32(t2, src2, 16, 16);
> + tcg_gen_mul_i32(t1, t1, t2);
> +
> + tcg_gen_concat_i32_i64(dst, t0, t1);
> +}
> +
> +static void gen_op_fmuld8sux16(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2)
> +{
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + TCGv_i32 t2 = tcg_temp_new_i32();
> +
> + /*
> + * The insn description talks about extracting the upper 8 bits
> + * of the signed 16-bit input rs1, performing the multiply, then
> + * shifting left by 8 bits. Instead, zap the lower 8 bits of
> + * the rs1 input, which avoids the need for two shifts.
Nice.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> + */
> + tcg_gen_ext16s_i32(t0, src1);
> + tcg_gen_andi_i32(t0, t0, ~0xff);
> + tcg_gen_ext16s_i32(t1, src2);
> + tcg_gen_mul_i32(t0, t0, t1);
> +
> + tcg_gen_sextract_i32(t1, src1, 16, 16);
> + tcg_gen_andi_i32(t1, t1, ~0xff);
> + tcg_gen_sextract_i32(t2, src2, 16, 16);
> + tcg_gen_mul_i32(t1, t1, t2);
> +
> + tcg_gen_concat_i32_i64(dst, t0, t1);
> +}
next prev parent reply other threads:[~2024-05-06 14:13 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-02 16:55 [PATCH v2 0/7] target/sparc: vis fixes Richard Henderson
2024-05-02 16:55 ` [PATCH v2 1/7] linux-user/sparc: Add more hwcap bits for sparc64 Richard Henderson
2024-05-02 16:55 ` [PATCH v2 2/7] target/sparc: Fix FEXPAND Richard Henderson
2024-05-03 18:34 ` Philippe Mathieu-Daudé
2024-05-02 16:55 ` [PATCH v2 3/7] target/sparc: Fix FMUL8x16 Richard Henderson
2024-05-03 18:31 ` Philippe Mathieu-Daudé
2024-05-02 16:55 ` [PATCH v2 4/7] target/sparc: Fix FMUL8x16A{U,L} Richard Henderson
2024-05-03 18:32 ` Philippe Mathieu-Daudé
2024-05-02 16:55 ` [PATCH v2 5/7] target/sparc: Fix FMULD8*X16 Richard Henderson
2024-05-06 14:12 ` Philippe Mathieu-Daudé [this message]
2024-05-02 16:55 ` [PATCH v2 6/7] target/sparc: Fix FPMERGE Richard Henderson
2024-05-03 18:27 ` Philippe Mathieu-Daudé
2024-05-02 16:55 ` [PATCH v2 7/7] target/sparc: Split out do_ms16b Richard Henderson
2024-05-03 19:11 ` Philippe Mathieu-Daudé
2024-05-03 19:12 ` Philippe Mathieu-Daudé
2024-05-03 18:18 ` [PATCH v2 0/7] target/sparc: vis fixes Philippe Mathieu-Daudé
2024-05-05 20:13 ` Mark Cave-Ayland
2024-05-05 20:05 ` Mark Cave-Ayland
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