From: Richard Henderson <richard.henderson@linaro.org>
To: Ruinland Chuan-Tzu Tsai <ruinland@andestech.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bin.meng@windriver.com, alistair23@gmail.com,
wangjunqiang@iscas.ac.cn, dylan@andestech.com,
alankao@andestech.com
Subject: Re: [RFC PATCH v3 2/2] Adding preliminary custom/vendor CSR handling mechanism
Date: Thu, 10 Jun 2021 09:19:38 -0700 [thread overview]
Message-ID: <c9d350fb-16bd-6dc6-41de-0516c046a244@linaro.org> (raw)
In-Reply-To: <20210610144424.8658-3-ruinland@andestech.com>
On 6/10/21 7:44 AM, Ruinland Chuan-Tzu Tsai wrote:
> --- /dev/null
> +++ b/target/riscv/andes_cpu_bits.h
> @@ -0,0 +1,113 @@
> +/* ========= AndeStar V5 machine mode CSRs ========= */
> --- /dev/null
> +++ b/target/riscv/csr_andes.inc.c
> @@ -0,0 +1,153 @@
> +/* Andes Custom Registers */
> --- /dev/null
> +++ b/target/riscv/custom_cpu_bits.h
> @@ -0,0 +1,3 @@
> +//XXX Maybe we should introduce a configure option to toggle different vendor
> +// CSR bits definition ?
> +#include "andes_cpu_bits.h"
All new files must have copyright+license boilerplate.
r~
next prev parent reply other threads:[~2021-06-10 16:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 14:44 [RFC PATCH v3 0/2] Proposing custom CSR handling logic Ruinland Chuan-Tzu Tsai
2021-06-10 14:44 ` [RFC PATCH v3 1/2] Adding Andes AX25 CPU model Ruinland Chuan-Tzu Tsai
2021-06-10 22:49 ` Alistair Francis
2021-06-10 23:22 ` Bin Meng
2021-06-10 14:44 ` [RFC PATCH v3 2/2] Adding preliminary custom/vendor CSR handling mechanism Ruinland Chuan-Tzu Tsai
2021-06-10 16:19 ` Richard Henderson [this message]
2021-06-10 22:57 ` Alistair Francis
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