From: Alistair Francis <alistair23@gmail.com>
To: Ruinland Chuan-Tzu Tsai <ruinland@andestech.com>
Cc: Dylan Jhong <dylan@andestech.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"Alan Quey-Liang Kao\(\(\(\(\(\(\(\(\(\(\)"
<alankao@andestech.com>, wangjunqiang <wangjunqiang@iscas.ac.cn>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [RFC PATCH v3 1/2] Adding Andes AX25 CPU model
Date: Fri, 11 Jun 2021 08:49:59 +1000 [thread overview]
Message-ID: <CAKmqyKP4c3tXmH2WR+712ek_WT-6uNVcf+saWthkUNmH+At0_w@mail.gmail.com> (raw)
In-Reply-To: <20210610144424.8658-2-ruinland@andestech.com>
On Fri, Jun 11, 2021 at 12:44 AM Ruinland Chuan-Tzu Tsai
<ruinland@andestech.com> wrote:
>
> From: Ruinaldn ChuanTzu Tsai <ruinland@andestech.com>
>
> Adding the skeleton of Andes Technology AX25 CPU model for the future commits,
> which will utilize custom/vendor CSR handling mechaism.
You are missing a SoB line.
See https://wiki.qemu.org/Contribute/SubmitAPatch for more details.
Alistair
> ---
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddea8fbeeb..4ae21cbf9b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -159,6 +159,13 @@ static void rv64_base_cpu_init(Object *obj)
> set_misa(env, RV64);
> }
>
> +static void ax25_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + set_priv_version(env, PRIV_VERSION_1_10_0);
> +}
> +
> static void rv64_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -705,6 +712,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
> #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0edb2826a2..bff9af7f3f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -37,6 +37,7 @@
> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
> --
> 2.31.1
>
next prev parent reply other threads:[~2021-06-10 22:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 14:44 [RFC PATCH v3 0/2] Proposing custom CSR handling logic Ruinland Chuan-Tzu Tsai
2021-06-10 14:44 ` [RFC PATCH v3 1/2] Adding Andes AX25 CPU model Ruinland Chuan-Tzu Tsai
2021-06-10 22:49 ` Alistair Francis [this message]
2021-06-10 23:22 ` Bin Meng
2021-06-10 14:44 ` [RFC PATCH v3 2/2] Adding preliminary custom/vendor CSR handling mechanism Ruinland Chuan-Tzu Tsai
2021-06-10 16:19 ` Richard Henderson
2021-06-10 22:57 ` Alistair Francis
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