From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
bin.meng@windriver.com, Alistair.Francis@wdc.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
Date: Thu, 10 Jun 2021 15:59:05 +0800 [thread overview]
Message-ID: <20210610075908.3305506-35-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com>
Two 32x32 results written directly to destation register or
as operands added to a 64-bit register.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 12 ++
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvp.c.inc | 13 ++
target/riscv/packed_helper.c | 182 ++++++++++++++++++++++++
4 files changed, 219 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 05f8f31367..aa80095e1d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1460,3 +1460,15 @@ DEF_HELPER_3(smtt32, i64, env, i64, i64)
DEF_HELPER_4(kmabb32, tl, env, tl, tl, tl)
DEF_HELPER_4(kmabt32, tl, env, tl, tl, tl)
DEF_HELPER_4(kmatt32, tl, env, tl, tl, tl)
+
+DEF_HELPER_3(kmda32, i64, env, i64, i64)
+DEF_HELPER_3(kmxda32, i64, env, i64, i64)
+DEF_HELPER_4(kmaxda32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmads32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmadrs32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmaxds32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmsda32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmsxda32, tl, env, tl, tl, tl)
+DEF_HELPER_3(smds32, i64, env, i64, i64)
+DEF_HELPER_3(smdrs32, i64, env, i64, i64)
+DEF_HELPER_3(smxds32, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index dec714a064..b9eeb57ca7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1083,3 +1083,15 @@ smtt32 0010100 ..... ..... 010 ..... 1110111 @r
kmabb32 0101101 ..... ..... 010 ..... 1110111 @r
kmabt32 0110101 ..... ..... 010 ..... 1110111 @r
kmatt32 0111101 ..... ..... 010 ..... 1110111 @r
+
+kmda32 0011100 ..... ..... 010 ..... 1110111 @r
+kmxda32 0011101 ..... ..... 010 ..... 1110111 @r
+kmaxda32 0100101 ..... ..... 010 ..... 1110111 @r
+kmads32 0101110 ..... ..... 010 ..... 1110111 @r
+kmadrs32 0110110 ..... ..... 010 ..... 1110111 @r
+kmaxds32 0111110 ..... ..... 010 ..... 1110111 @r
+kmsda32 0100110 ..... ..... 010 ..... 1110111 @r
+kmsxda32 0100111 ..... ..... 010 ..... 1110111 @r
+smds32 0101100 ..... ..... 010 ..... 1110111 @r
+smdrs32 0110100 ..... ..... 010 ..... 1110111 @r
+smxds32 0111100 ..... ..... 010 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 2de81abbb8..48bcf37e36 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1131,3 +1131,16 @@ GEN_RVP64_R_OOL(smtt32);
GEN_RVP64_R_ACC_OOL(kmabb32);
GEN_RVP64_R_ACC_OOL(kmabt32);
GEN_RVP64_R_ACC_OOL(kmatt32);
+
+/* (RV64 Only) 32-bit Parallel Multiply & Add Instructions */
+GEN_RVP64_R_OOL(kmda32);
+GEN_RVP64_R_OOL(kmxda32);
+GEN_RVP64_R_ACC_OOL(kmaxda32);
+GEN_RVP64_R_ACC_OOL(kmads32);
+GEN_RVP64_R_ACC_OOL(kmadrs32);
+GEN_RVP64_R_ACC_OOL(kmaxds32);
+GEN_RVP64_R_ACC_OOL(kmsda32);
+GEN_RVP64_R_ACC_OOL(kmsxda32);
+GEN_RVP64_R_OOL(smds32);
+GEN_RVP64_R_OOL(smdrs32);
+GEN_RVP64_R_OOL(smxds32);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 3c05c748c4..834e7dbebb 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3613,3 +3613,185 @@ static inline void do_kmatt32(CPURISCVState *env, void *vd, void *va,
}
RVPR_ACC(kmatt32, 1, 8);
+
+/* (RV64 Only) 32-bit Parallel Multiply & Add Instructions */
+static inline void do_kmda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ if (a[H4(i)] == INT32_MIN && b[H4(i)] == INT32_MIN &&
+ a[H4(i + 1)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ *d = INT64_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H4(i)] * b[H4(i)] +
+ (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+ }
+}
+
+RVPR64_64_64(kmda32, 1, 8);
+
+static inline void do_kmxda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ if (a[H4(i)] == INT32_MIN && b[H4(i)] == INT32_MIN &&
+ a[H4(i + 1)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ *d = INT64_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H4(i)] * b[H4(i + 1)] +
+ (int64_t)a[H4(i + 1)] * b[H4(i)];
+ }
+}
+
+RVPR64_64_64(kmxda32, 1, 8);
+
+static inline void do_kmaxda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t p1, p2;
+ p1 = (int64_t)a[H4(i)] * b[H4(i + 1)];
+ p2 = (int64_t)a[H4(i + 1)] * b[H4(i)];
+
+ if (a[H4(i)] == INT32_MIN && a[H4(i + 1)] == INT32_MIN &&
+ b[H4(i)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ if (*d < 0) {
+ *d = (INT64_MAX + *c) + 1ll;
+ } else {
+ env->vxsat = 0x1;
+ *d = INT64_MAX;
+ }
+ } else {
+ *d = sadd64(env, 0, p1 + p2, *c);
+ }
+}
+
+RVPR_ACC(kmaxda32, 1, 8);
+
+static inline void do_kmads32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t0, t1;
+ t1 = (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+ t0 = (int64_t)a[H4(i)] * b[H4(i)];
+
+ *d = sadd64(env, 0, t1 - t0, *c);
+}
+
+RVPR_ACC(kmads32, 1, 8);
+
+static inline void do_kmadrs32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t0, t1;
+ t1 = (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+ t0 = (int64_t)a[H4(i)] * b[H4(i)];
+
+ *d = sadd64(env, 0, t0 - t1, *c);
+}
+
+RVPR_ACC(kmadrs32, 1, 8);
+
+static inline void do_kmaxds32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t01, t10;
+ t01 = (int64_t)a[H4(i)] * b[H4(i + 1)];
+ t10 = (int64_t)a[H4(i + 1)] * b[H4(i)];
+
+ *d = sadd64(env, 0, t10 - t01, *c);
+}
+
+RVPR_ACC(kmaxds32, 1, 8);
+
+static inline void do_kmsda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t0, t1;
+ t0 = (int64_t)a[H4(i)] * b[H4(i)];
+ t1 = (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+
+ if (a[H4(i)] == INT32_MIN && a[H4(i + 1)] == INT32_MIN &&
+ b[H4(i)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ if (*c < 0) {
+ env->vxsat = 0x1;
+ *d = INT64_MIN;
+ } else {
+ *d = *c - 1ll - INT64_MAX;
+ }
+ } else {
+ *d = ssub64(env, 0, *c, t0 + t1);
+ }
+}
+
+RVPR_ACC(kmsda32, 1, 8);
+
+static inline void do_kmsxda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t01, t10;
+ t10 = (int64_t)a[H4(i + 1)] * b[H4(i)];
+ t01 = (int64_t)a[H4(i)] * b[H4(i + 1)];
+
+ if (a[H4(i)] == INT32_MIN && a[H4(i + 1)] == INT32_MIN &&
+ b[H4(i)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ if (*c < 0) {
+ env->vxsat = 0x1;
+ *d = INT64_MIN;
+ } else {
+ *d = *c - 1ll - INT64_MAX;
+ }
+ } else {
+ *d = ssub64(env, 0, *c, t10 + t01);
+ }
+}
+
+RVPR_ACC(kmsxda32, 1, 8);
+
+static inline void do_smds32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ *d = (int64_t)a[H4(i + 1)] * b[H4(i + 1)] -
+ (int64_t)a[H4(i)] * b[H4(i)];
+}
+
+RVPR64_64_64(smds32, 1, 8);
+
+static inline void do_smdrs32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ *d = (int64_t)a[H4(i)] * b[H4(i)] -
+ (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+}
+
+RVPR64_64_64(smdrs32, 1, 8);
+
+static inline void do_smxds32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ *d = (int64_t)a[H4(i + 1)] * b[H4(i)] -
+ (int64_t)a[H4(i)] * b[H4(i + 1)];
+}
+
+RVPR64_64_64(smxds32, 1, 8);
--
2.25.1
next prev parent reply other threads:[~2021-06-10 8:37 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-06-10 18:00 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-06-10 19:39 ` Richard Henderson
2021-06-11 4:36 ` LIU Zhiwei
2021-06-24 6:05 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-06-10 19:44 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei [this message]
2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-06-14 22:55 ` [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 no-reply
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