From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
bin.meng@windriver.com, Alistair.Francis@wdc.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
Date: Thu, 10 Jun 2021 15:59:02 +0800 [thread overview]
Message-ID: <20210610075908.3305506-32-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com>
Q15 saturation limits the result to the range [INT16_MIN, INT16_MAX].
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 10 ++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvp.c.inc | 19 ++++
target/riscv/packed_helper.c | 139 ++++++++++++++++++++++++
4 files changed, 178 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d992859747..5edaf389e4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1443,3 +1443,13 @@ DEF_HELPER_3(umin32, i64, env, i64, i64)
DEF_HELPER_3(smax32, i64, env, i64, i64)
DEF_HELPER_3(umax32, i64, env, i64, i64)
DEF_HELPER_2(kabs32, tl, env, tl)
+
+DEF_HELPER_3(khmbb16, i64, env, i64, i64)
+DEF_HELPER_3(khmbt16, i64, env, i64, i64)
+DEF_HELPER_3(khmtt16, i64, env, i64, i64)
+DEF_HELPER_3(kdmbb16, i64, env, i64, i64)
+DEF_HELPER_3(kdmbt16, i64, env, i64, i64)
+DEF_HELPER_3(kdmtt16, i64, env, i64, i64)
+DEF_HELPER_4(kdmabb16, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmabt16, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmatt16, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ee5f855f28..a7b5643d5f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1066,3 +1066,13 @@ umin32 1010000 ..... ..... 010 ..... 1110111 @r
smax32 1001001 ..... ..... 010 ..... 1110111 @r
umax32 1010001 ..... ..... 010 ..... 1110111 @r
kabs32 1010110 10010 ..... 000 ..... 1110111 @r2
+
+khmbb16 1101110 ..... ..... 001 ..... 1110111 @r
+khmbt16 1110110 ..... ..... 001 ..... 1110111 @r
+khmtt16 1111110 ..... ..... 001 ..... 1110111 @r
+kdmbb16 1101101 ..... ..... 001 ..... 1110111 @r
+kdmbt16 1110101 ..... ..... 001 ..... 1110111 @r
+kdmtt16 1111101 ..... ..... 001 ..... 1110111 @r
+kdmabb16 1101100 ..... ..... 001 ..... 1110111 @r
+kdmabt16 1110100 ..... ..... 001 ..... 1110111 @r
+kdmatt16 1111100 ..... ..... 001 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 77586e07e4..aa97161697 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1103,3 +1103,22 @@ static bool trans_##NAME(DisasContext *s, arg_r2 *a) \
}
GEN_RVP64_R2_OOL(kabs32);
+
+/* (RV64 Only) SIMD Q15 saturating Multiply Instructions */
+GEN_RVP64_R_OOL(khmbb16);
+GEN_RVP64_R_OOL(khmbt16);
+GEN_RVP64_R_OOL(khmtt16);
+GEN_RVP64_R_OOL(kdmbb16);
+GEN_RVP64_R_OOL(kdmbt16);
+GEN_RVP64_R_OOL(kdmtt16);
+
+#define GEN_RVP64_R_ACC_OOL(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r *a) \
+{ \
+ REQUIRE_64BIT(s); \
+ return r_acc_ool(s, a, gen_helper_##NAME); \
+}
+
+GEN_RVP64_R_ACC_OOL(kdmabb16);
+GEN_RVP64_R_ACC_OOL(kdmabt16);
+GEN_RVP64_R_ACC_OOL(kdmatt16);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index a808dae9d8..32e0af2ef6 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3422,3 +3422,142 @@ static inline void do_kabs32(CPURISCVState *env, void *vd, void *va, uint8_t i)
}
RVPR2(kabs32, 1, 4);
+
+/* (RV64 Only) SIMD Q15 saturating Multiply Instructions */
+static inline void do_khmbb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i)] * b[H2(i)] >> 15, 15);
+}
+
+RVPR64_64_64(khmbb16, 2, 2);
+
+static inline void do_khmbt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i)] * b[H2(i + 1)] >> 15, 15);
+}
+
+RVPR64_64_64(khmbt16, 2, 2);
+
+static inline void do_khmtt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i + 1)] * b[H2(i + 1)] >> 15, 15);
+}
+
+RVPR64_64_64(khmtt16, 2, 2);
+
+static inline void do_kdmbb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+}
+
+RVPR64_64_64(kdmbb16, 2, 2);
+
+static inline void do_kdmbt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR64_64_64(kdmbt16, 2, 2);
+
+static inline void do_kdmtt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR64_64_64(kdmtt16, 2, 2);
+
+static inline void do_kdmabb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+ d[H4(i / 2)] = sadd32(env, 0, c[H4(i / 2)], m0);
+}
+
+RVPR_ACC(kdmabb16, 2, 2);
+
+static inline void do_kdmabt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+ d[H4(i / 2)] = sadd32(env, 0, c[H4(i / 2)], m0);
+}
+
+RVPR_ACC(kdmabt16, 2, 2);
+
+static inline void do_kdmatt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+ d[H4(i / 2)] = sadd32(env, 0, c[H4(i / 2)], m0);
+}
+
+RVPR_ACC(kdmatt16, 2, 2);
--
2.25.1
next prev parent reply other threads:[~2021-06-10 8:18 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-06-10 18:00 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-06-10 19:39 ` Richard Henderson
2021-06-11 4:36 ` LIU Zhiwei
2021-06-24 6:05 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-06-10 19:44 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei [this message]
2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-06-14 22:55 ` [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 no-reply
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