From: no-reply@patchew.org
To: zhiwei_liu@c-sky.com
Cc: qemu-riscv@nongnu.org, bin.meng@windriver.com,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
palmer@dabbelt.com, Alistair.Francis@wdc.com,
zhiwei_liu@c-sky.com
Subject: Re: [PATCH v2 00/37] target/riscv: support packed extension v0.9.4
Date: Mon, 14 Jun 2021 15:55:57 -0700 (PDT) [thread overview]
Message-ID: <162371135630.2358.14618248358183649201@7c66fb7bc3ab> (raw)
In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com>
Patchew URL: https://patchew.org/QEMU/20210610075908.3305506-1-zhiwei_liu@c-sky.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210610075908.3305506-1-zhiwei_liu@c-sky.com
Subject: [PATCH v2 00/37] target/riscv: support packed extension v0.9.4
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
58bab55 target/riscv: configure and turn on packed extension from command line
aaa9443 target/riscv: RV64 Only 32-bit Packing Instructions
fd98368 target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
13ee829 target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
a45bf09 target/riscv: RV64 Only 32-bit Multiply & Add Instructions
afa9d9f target/riscv: RV64 Only 32-bit Multiply Instructions
5e47cf9 target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
0707fb2 target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
9103b42 target/riscv: RV64 Only SIMD 32-bit Shift Instructions
aa8562e target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
4e3c751 target/riscv: Non-SIMD Miscellaneous Instructions
98463d7 target/riscv: 32-bit Computation Instructions
a2b5fa4 target/riscv: Non-SIMD Q31 saturation ALU Instructions
5ac11aa target/riscv: Non-SIMD Q15 saturation ALU Instructions
8f8cc98 target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
562fe16 target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
abd68e9 target/riscv: 64-bit Add/Subtract Instructions
1101a08 target/riscv: 8-bit Multiply with 32-bit Add Instructions
cade413 target/riscv: Partial-SIMD Miscellaneous Instructions
868fc8a target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
55ea8d5 target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
fc7375d target/riscv: Signed MSW 32x16 Multiply and Add Instructions
14d0690 target/riscv: Signed MSW 32x32 Multiply and Add Instructions
75852f9 target/riscv: 16-bit Packing Instructions
4c0f92a target/riscv: 8-bit Unpacking Instructions
da3eb1d target/riscv: SIMD 8-bit Miscellaneous Instructions
cda90fe target/riscv: SIMD 16-bit Miscellaneous Instructions
2c1cebb target/riscv: SIMD 8-bit Multiply Instructions
ea6538c target/riscv: SIMD 16-bit Multiply Instructions
e6d145d target/riscv: SIMD 8-bit Compare Instructions
c7dc098 target/riscv: SIMD 16-bit Compare Instructions
98fdd40 target/riscv: SIMD 8-bit Shift Instructions
161cf36 target/riscv: SIMD 16-bit Shift Instructions
52b81ce target/riscv: 8-bit Addition & Subtraction Instruction
51a264e target/riscv: 16-bit Addition & Subtraction Instructions
9bfdab5 target/riscv: Make the vector helper functions public
8966803 target/riscv: implementation-defined constant parameters
=== OUTPUT BEGIN ===
1/37 Checking commit 896680352f63 (target/riscv: implementation-defined constant parameters)
2/37 Checking commit 9bfdab58457e (target/riscv: Make the vector helper functions public)
3/37 Checking commit 51a264e82cf5 (target/riscv: 16-bit Addition & Subtraction Instructions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#132:
new file mode 100644
ERROR: space prohibited after that '*' (ctx:BxW)
#172: FILE: target/riscv/insn_trans/trans_rvp.c.inc:36:
+ void (* vecop)(TCGv, TCGv, TCGv),
^
ERROR: space prohibited after that '*' (ctx:BxW)
#173: FILE: target/riscv/insn_trans/trans_rvp.c.inc:37:
+ void (* op)(TCGv, TCGv, TCGv))
^
ERROR: space prohibited after that '*' (ctx:BxW)
#198: FILE: target/riscv/insn_trans/trans_rvp.c.inc:62:
+r_ool(DisasContext *ctx, arg_r *a, void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv))
^
total: 3 errors, 1 warnings, 617 lines checked
Patch 3/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/37 Checking commit 52b81cea79fe (target/riscv: 8-bit Addition & Subtraction Instruction)
5/37 Checking commit 161cf360f41e (target/riscv: SIMD 16-bit Shift Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#138: FILE: target/riscv/insn_trans/trans_rvp.c.inc:144:
+ void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv))
^
ERROR: space prohibited after that '*' (ctx:BxW)
#158: FILE: target/riscv/insn_trans/trans_rvp.c.inc:164:
+ void (* vecop)(TCGv, TCGv, target_long),
^
ERROR: space prohibited after that '*' (ctx:BxW)
#159: FILE: target/riscv/insn_trans/trans_rvp.c.inc:165:
+ void (* op)(TCGv, TCGv_ptr, TCGv, TCGv))
^
total: 3 errors, 0 warnings, 289 lines checked
Patch 5/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/37 Checking commit 98fdd4058bd6 (target/riscv: SIMD 8-bit Shift Instructions)
7/37 Checking commit c7dc0984c42d (target/riscv: SIMD 16-bit Compare Instructions)
8/37 Checking commit e6d145d8c6e2 (target/riscv: SIMD 8-bit Compare Instructions)
9/37 Checking commit ea6538c95033 (target/riscv: SIMD 16-bit Multiply Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#91: FILE: target/riscv/insn_trans/trans_rvp.c.inc:253:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv, TCGv))
^
total: 1 errors, 0 warnings, 199 lines checked
Patch 9/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/37 Checking commit 2c1cebb7751d (target/riscv: SIMD 8-bit Multiply Instructions)
11/37 Checking commit cda90fe68120 (target/riscv: SIMD 16-bit Miscellaneous Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#79: FILE: target/riscv/insn_trans/trans_rvp.c.inc:309:
+ void (* fn)(TCGv, TCGv_ptr, TCGv))
^
total: 1 errors, 0 warnings, 233 lines checked
Patch 11/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/37 Checking commit da3eb1d28281 (target/riscv: SIMD 8-bit Miscellaneous Instructions)
13/37 Checking commit 4c0f92ad768c (target/riscv: 8-bit Unpacking Instructions)
14/37 Checking commit 75852f9829dd (target/riscv: 16-bit Packing Instructions)
15/37 Checking commit 14d069035135 (target/riscv: Signed MSW 32x32 Multiply and Add Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#69: FILE: target/riscv/insn_trans/trans_rvp.c.inc:379:
+ void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv, TCGv))
^
total: 1 errors, 0 warnings, 183 lines checked
Patch 15/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/37 Checking commit fc7375de7797 (target/riscv: Signed MSW 32x16 Multiply and Add Instructions)
17/37 Checking commit 55ea8d559755 (target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions)
18/37 Checking commit 868fc8a71557 (target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#50: FILE: target/riscv/insn_trans/trans_rvp.c.inc:458:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv))
^
total: 1 errors, 0 warnings, 92 lines checked
Patch 18/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/37 Checking commit cade413e7d67 (target/riscv: Partial-SIMD Miscellaneous Instructions)
20/37 Checking commit 1101a08fa021 (target/riscv: 8-bit Multiply with 32-bit Add Instructions)
21/37 Checking commit abd68e9846f7 (target/riscv: 64-bit Add/Subtract Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#71: FILE: target/riscv/insn_trans/trans_rvp.c.inc:526:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
^
total: 1 errors, 0 warnings, 240 lines checked
Patch 21/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
22/37 Checking commit 562fe1664758 (target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#67: FILE: target/riscv/insn_trans/trans_rvp.c.inc:599:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv, TCGv, TCGv_i64))
^
total: 1 errors, 0 warnings, 252 lines checked
Patch 22/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
23/37 Checking commit 8f8cc98490dd (target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions)
24/37 Checking commit 5ac11aaba982 (target/riscv: Non-SIMD Q15 saturation ALU Instructions)
25/37 Checking commit a2b5fa48ee23 (target/riscv: Non-SIMD Q31 saturation ALU Instructions)
26/37 Checking commit 98463d7bddc4 (target/riscv: 32-bit Computation Instructions)
27/37 Checking commit 4e3c7519d03b (target/riscv: Non-SIMD Miscellaneous Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#103: FILE: target/riscv/insn_trans/trans_rvp.c.inc:721:
+ void (* fn)(TCGv, TCGv_ptr, TCGv_i64, TCGv))
^
ERROR: space prohibited after that '*' (ctx:BxW)
#151: FILE: target/riscv/insn_trans/trans_rvp.c.inc:769:
+ void (* fn)(TCGv, TCGv_ptr, TCGv_i64, TCGv))
^
total: 2 errors, 0 warnings, 376 lines checked
Patch 27/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
28/37 Checking commit aa8562e69e4f (target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#144: FILE: target/riscv/insn_trans/trans_rvp.c.inc:969:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
^
total: 1 errors, 0 warnings, 449 lines checked
Patch 28/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/37 Checking commit 9103b42ea0f6 (target/riscv: RV64 Only SIMD 32-bit Shift Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#71: FILE: target/riscv/insn_trans/trans_rvp.c.inc:1040:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
^
total: 1 errors, 0 warnings, 195 lines checked
Patch 29/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
30/37 Checking commit 0707fb22513f (target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions)
31/37 Checking commit 5e47cf943de0 (target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions)
32/37 Checking commit afa9d9f289b8 (target/riscv: RV64 Only 32-bit Multiply Instructions)
33/37 Checking commit a45bf09dd5f8 (target/riscv: RV64 Only 32-bit Multiply & Add Instructions)
34/37 Checking commit 13ee829e5c05 (target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions)
35/37 Checking commit fd983689c420 (target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions)
36/37 Checking commit aaa9443b6f93 (target/riscv: RV64 Only 32-bit Packing Instructions)
37/37 Checking commit 58bab55e2bde (target/riscv: configure and turn on packed extension from command line)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210610075908.3305506-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
prev parent reply other threads:[~2021-06-14 22:57 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-06-10 18:00 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-06-10 19:39 ` Richard Henderson
2021-06-11 4:36 ` LIU Zhiwei
2021-06-24 6:05 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-06-10 19:44 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-06-14 22:55 ` no-reply [this message]
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