From: Georgi Djakov <djakov@kernel.org> To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, matthias.bgg@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, keescook@chromium.org, gustavoars@kernel.org, henryc.chen@mediatek.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, amergnat@baylibre.com, Dawei Chien <dawei.chien@mediatek.com> Subject: Re: [PATCH v5 4/7] soc: mediatek: Add MediaTek DVFS Resource Collector (DVFSRC) driver Date: Mon, 29 Apr 2024 17:13:13 +0300 [thread overview] Message-ID: <c3531f5f-7aaa-4363-8bfe-ac90521d7a0e@kernel.org> (raw) In-Reply-To: <20240424095416.1105639-5-angelogioacchino.delregno@collabora.com> On 24.04.24 12:54, AngeloGioacchino Del Regno wrote: > The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a > Hardware module used to collect all the requests from both software and the > various remote processors embedded into the SoC and decide about a minimum > operating voltage and a minimum DRAM frequency to fulfill those requests in > an effort to provide the best achievable performance per watt. > > This hardware IP is capable of transparently performing direct register R/W > on all of the DVFSRC-controlled regulators and SoC bandwidth knobs. > > This driver includes support for MT8183, MT8192 and MT8195. > > Co-Developed-by: Dawei Chien <dawei.chien@mediatek.com> > [Angelo: Partial refactoring and cleanups] > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Thanks for reviving this patchset! > --- > drivers/soc/mediatek/Kconfig | 11 + > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mtk-dvfsrc.c | 551 +++++++++++++++++++++++ > include/linux/soc/mediatek/dvfsrc.h | 36 ++ > include/linux/soc/mediatek/mtk_sip_svc.h | 3 + > 5 files changed, 602 insertions(+) > create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c > create mode 100644 include/linux/soc/mediatek/dvfsrc.h > [..] > +++ b/drivers/soc/mediatek/mtk-dvfsrc.c > @@ -0,0 +1,551 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 MediaTek Inc. > + * Copyright (c) 2024 Collabora Ltd. > + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + */ > + > +#include <linux/arm-smccc.h> > +#include <linux/bitfield.h> > +#include <linux/iopoll.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_platform.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/dvfsrc.h> > +#include <linux/soc/mediatek/mtk_sip_svc.h> > + > +/* DVFSRC_LEVEL */ > +#define DVFSRC_V1_LEVEL_TARGET_LEVEL GENMASK(15, 0) > +#define DVFSRC_TGT_LEVEL_IDLE 0x00 > +#define DVFSRC_V1_LEVEL_CURRENT_LEVEL GENMASK(31, 16) > + > +/* DVFSRC_SW_REQ, DVFSRC_SW_REQ2 */ > +#define DVFSRC_V1_SW_REQ2_DRAM_LEVEL GENMASK(1, 0) > +#define DVFSRC_V1_SW_REQ2_VCORE_LEVEL GENMASK(3, 2) > + > +#define DVFSRC_V2_SW_REQ_DRAM_LEVEL GENMASK(3, 0) > +#define DVFSRC_V2_SW_REQ_VCORE_LEVEL GENMASK(6, 4) > + > +/* DVFSRC_VCORE */ > +#define DVFSRC_V2_VCORE_REQ_VSCP_LEVEL GENMASK(14, 12) > + > +#define KBPS_TO_MBPS(x) ((x) / 1000) > + > +#define DVFSRC_POLL_TIMEOUT_US 1000 > +#define STARTUP_TIME_US 1 > + > +#define MTK_SIP_DVFSRC_INIT 0x0 > +#define MTK_SIP_DVFSRC_START 0x1 > + > +struct dvfsrc_bw_constraints { > + u16 max_dram_nom_bw; > + u16 max_dram_peak_bw; > + u16 max_dram_hrt_bw; > +}; > + > +struct dvfsrc_opp { > + u32 vcore_opp; > + u32 dram_opp; > +}; > + > +struct dvfsrc_opp_desc { > + const struct dvfsrc_opp *opps; > + u32 num_opp; > +}; > + > +struct dvfsrc_soc_data; > +struct mtk_dvfsrc { > + struct device *dev; > + struct platform_device *icc; > + struct platform_device *regulator; > + const struct dvfsrc_soc_data *dvd; > + const struct dvfsrc_opp_desc *curr_opps; > + void __iomem *regs; > + int dram_type; > +}; > + > +struct dvfsrc_soc_data { > + const int *regs; > + const struct dvfsrc_opp_desc *opps_desc; > + u32 (*get_target_level)(struct mtk_dvfsrc *dvfsrc); > + u32 (*get_current_level)(struct mtk_dvfsrc *dvfsrc); > + u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc); > + u32 (*get_vscp_level)(struct mtk_dvfsrc *dvfsrc); > + void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); > + void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); > + void (*set_dram_hrt_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); > + void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + const struct dvfsrc_bw_constraints *bw_constraints; > +}; > + > +static u32 dvfsrc_readl(struct mtk_dvfsrc *dvfs, u32 offset) > +{ > + return readl(dvfs->regs + dvfs->dvd->regs[offset]); > +} > + > +static void dvfsrc_writel(struct mtk_dvfsrc *dvfs, u32 offset, u32 val) > +{ > + writel(val, dvfs->regs + dvfs->dvd->regs[offset]); > +} > + > +#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \ > + dvfsrc_writel(dvfs, offset, \ > + (dvfsrc_readl(dvfs, offset) & ~(mask << shift)) | (val << shift)) Nit: The above macro seems unused? BR, Georgi > +enum dvfsrc_regs { > + DVFSRC_SW_REQ, > + DVFSRC_SW_REQ2, > + DVFSRC_LEVEL, > + DVFSRC_TARGET_LEVEL, > + DVFSRC_SW_BW, > + DVFSRC_SW_PEAK_BW, > + DVFSRC_SW_HRT_BW, > + DVFSRC_VCORE, > + DVFSRC_REGS_MAX, > +}; > +
WARNING: multiple messages have this Message-ID (diff)
From: Georgi Djakov <djakov@kernel.org> To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, matthias.bgg@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, keescook@chromium.org, gustavoars@kernel.org, henryc.chen@mediatek.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, amergnat@baylibre.com, Dawei Chien <dawei.chien@mediatek.com> Subject: Re: [PATCH v5 4/7] soc: mediatek: Add MediaTek DVFS Resource Collector (DVFSRC) driver Date: Mon, 29 Apr 2024 17:13:13 +0300 [thread overview] Message-ID: <c3531f5f-7aaa-4363-8bfe-ac90521d7a0e@kernel.org> (raw) In-Reply-To: <20240424095416.1105639-5-angelogioacchino.delregno@collabora.com> On 24.04.24 12:54, AngeloGioacchino Del Regno wrote: > The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a > Hardware module used to collect all the requests from both software and the > various remote processors embedded into the SoC and decide about a minimum > operating voltage and a minimum DRAM frequency to fulfill those requests in > an effort to provide the best achievable performance per watt. > > This hardware IP is capable of transparently performing direct register R/W > on all of the DVFSRC-controlled regulators and SoC bandwidth knobs. > > This driver includes support for MT8183, MT8192 and MT8195. > > Co-Developed-by: Dawei Chien <dawei.chien@mediatek.com> > [Angelo: Partial refactoring and cleanups] > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Thanks for reviving this patchset! > --- > drivers/soc/mediatek/Kconfig | 11 + > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mtk-dvfsrc.c | 551 +++++++++++++++++++++++ > include/linux/soc/mediatek/dvfsrc.h | 36 ++ > include/linux/soc/mediatek/mtk_sip_svc.h | 3 + > 5 files changed, 602 insertions(+) > create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c > create mode 100644 include/linux/soc/mediatek/dvfsrc.h > [..] > +++ b/drivers/soc/mediatek/mtk-dvfsrc.c > @@ -0,0 +1,551 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 MediaTek Inc. > + * Copyright (c) 2024 Collabora Ltd. > + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + */ > + > +#include <linux/arm-smccc.h> > +#include <linux/bitfield.h> > +#include <linux/iopoll.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_platform.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/dvfsrc.h> > +#include <linux/soc/mediatek/mtk_sip_svc.h> > + > +/* DVFSRC_LEVEL */ > +#define DVFSRC_V1_LEVEL_TARGET_LEVEL GENMASK(15, 0) > +#define DVFSRC_TGT_LEVEL_IDLE 0x00 > +#define DVFSRC_V1_LEVEL_CURRENT_LEVEL GENMASK(31, 16) > + > +/* DVFSRC_SW_REQ, DVFSRC_SW_REQ2 */ > +#define DVFSRC_V1_SW_REQ2_DRAM_LEVEL GENMASK(1, 0) > +#define DVFSRC_V1_SW_REQ2_VCORE_LEVEL GENMASK(3, 2) > + > +#define DVFSRC_V2_SW_REQ_DRAM_LEVEL GENMASK(3, 0) > +#define DVFSRC_V2_SW_REQ_VCORE_LEVEL GENMASK(6, 4) > + > +/* DVFSRC_VCORE */ > +#define DVFSRC_V2_VCORE_REQ_VSCP_LEVEL GENMASK(14, 12) > + > +#define KBPS_TO_MBPS(x) ((x) / 1000) > + > +#define DVFSRC_POLL_TIMEOUT_US 1000 > +#define STARTUP_TIME_US 1 > + > +#define MTK_SIP_DVFSRC_INIT 0x0 > +#define MTK_SIP_DVFSRC_START 0x1 > + > +struct dvfsrc_bw_constraints { > + u16 max_dram_nom_bw; > + u16 max_dram_peak_bw; > + u16 max_dram_hrt_bw; > +}; > + > +struct dvfsrc_opp { > + u32 vcore_opp; > + u32 dram_opp; > +}; > + > +struct dvfsrc_opp_desc { > + const struct dvfsrc_opp *opps; > + u32 num_opp; > +}; > + > +struct dvfsrc_soc_data; > +struct mtk_dvfsrc { > + struct device *dev; > + struct platform_device *icc; > + struct platform_device *regulator; > + const struct dvfsrc_soc_data *dvd; > + const struct dvfsrc_opp_desc *curr_opps; > + void __iomem *regs; > + int dram_type; > +}; > + > +struct dvfsrc_soc_data { > + const int *regs; > + const struct dvfsrc_opp_desc *opps_desc; > + u32 (*get_target_level)(struct mtk_dvfsrc *dvfsrc); > + u32 (*get_current_level)(struct mtk_dvfsrc *dvfsrc); > + u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc); > + u32 (*get_vscp_level)(struct mtk_dvfsrc *dvfsrc); > + void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); > + void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); > + void (*set_dram_hrt_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); > + void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level); > + const struct dvfsrc_bw_constraints *bw_constraints; > +}; > + > +static u32 dvfsrc_readl(struct mtk_dvfsrc *dvfs, u32 offset) > +{ > + return readl(dvfs->regs + dvfs->dvd->regs[offset]); > +} > + > +static void dvfsrc_writel(struct mtk_dvfsrc *dvfs, u32 offset, u32 val) > +{ > + writel(val, dvfs->regs + dvfs->dvd->regs[offset]); > +} > + > +#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \ > + dvfsrc_writel(dvfs, offset, \ > + (dvfsrc_readl(dvfs, offset) & ~(mask << shift)) | (val << shift)) Nit: The above macro seems unused? BR, Georgi > +enum dvfsrc_regs { > + DVFSRC_SW_REQ, > + DVFSRC_SW_REQ2, > + DVFSRC_LEVEL, > + DVFSRC_TARGET_LEVEL, > + DVFSRC_SW_BW, > + DVFSRC_SW_PEAK_BW, > + DVFSRC_SW_HRT_BW, > + DVFSRC_VCORE, > + DVFSRC_REGS_MAX, > +}; > + _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-04-29 14:13 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-24 9:54 [PATCH v5 0/7] MediaTek DVFSRC Bus Bandwidth and Regulator knobs AngeloGioacchino Del Regno 2024-04-24 9:54 ` AngeloGioacchino Del Regno 2024-04-24 9:54 ` [PATCH v5 1/7] dt-bindings: regulator: Add bindings for MediaTek DVFSRC Regulators AngeloGioacchino Del Regno 2024-04-24 9:54 ` AngeloGioacchino Del Regno 2024-04-24 9:54 ` [PATCH v5 2/7] dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings AngeloGioacchino Del Regno 2024-04-24 9:54 ` AngeloGioacchino Del Regno 2024-04-24 9:54 ` [PATCH v5 3/7] dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195 AngeloGioacchino Del Regno 2024-04-24 9:54 ` AngeloGioacchino Del Regno 2024-04-24 9:54 ` [PATCH v5 4/7] soc: mediatek: Add MediaTek DVFS Resource Collector (DVFSRC) driver AngeloGioacchino Del Regno 2024-04-24 9:54 ` AngeloGioacchino Del Regno 2024-04-24 19:04 ` Nathan Chancellor 2024-04-24 19:04 ` Nathan Chancellor 2024-04-29 8:08 ` AngeloGioacchino Del Regno 2024-04-29 8:08 ` AngeloGioacchino Del Regno 2024-04-29 14:13 ` Georgi Djakov [this message] 2024-04-29 14:13 ` Georgi Djakov 2024-04-24 9:54 ` [PATCH v5 5/7] regulator: Remove mtk-dvfsrc-regulator.c AngeloGioacchino Del Regno 2024-04-24 9:54 ` AngeloGioacchino Del Regno 2024-04-24 9:54 ` [PATCH v5 6/7] regulator: Add refactored mtk-dvfsrc-regulator driver AngeloGioacchino Del Regno 2024-04-24 9:54 ` AngeloGioacchino Del Regno 2024-04-24 10:35 ` Christophe JAILLET 2024-04-24 10:35 ` Christophe JAILLET 2024-04-24 12:53 ` AngeloGioacchino Del Regno 2024-04-24 12:53 ` AngeloGioacchino Del Regno 2024-04-24 12:54 ` AngeloGioacchino Del Regno 2024-04-24 12:54 ` AngeloGioacchino Del Regno 2024-04-24 9:54 ` [PATCH v5 7/7] interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect driver AngeloGioacchino Del Regno 2024-04-24 9:54 ` AngeloGioacchino Del Regno 2024-05-03 11:53 ` Georgi Djakov 2024-05-03 11:53 ` Georgi Djakov 2024-05-06 10:49 ` AngeloGioacchino Del Regno 2024-05-06 10:49 ` AngeloGioacchino Del Regno
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