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From: "Ramon Fried" <rfried.dev@gmail.com>
To: "Ramon Fried" <rfried.dev@gmail.com>,
	"Heinrich Schuchardt" <xypron.glpk@gmx.de>
Cc: "Joe Hershberger" <joe.hershberger@ni.com>,
	"U-Boot Mailing List" <u-boot@lists.denx.de>,
	"Jagan Teki" <jagan@amarulasolutions.com>,
	"Andre Przywara" <andre.przywara@arm.com>
Subject: Re: [PATCH 1/1] net: sun8i-emac: fix MDIO frequency
Date: Sat, 12 Jun 2021 21:41:32 +0300	[thread overview]
Message-ID: <CC1UZ40R2AQ8.1598HR3VOBULL@stdcall-pc> (raw)
In-Reply-To: <CAGi-RUL8+0nZ7sSZKueFWT=Q1uK=16LOCKXGEyD2VtT5yzuq_Q@mail.gmail.com>

On Thu Jun 10, 2021 at 8:48 AM IDT, Ramon Fried wrote:
> On Thu, Jun 3, 2021 at 10:52 AM Heinrich Schuchardt <xypron.glpk@gmx.de>
> wrote:
> >
> > Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to
> > network failure on the OrangePi PC.
> >
> >     => dhcp
> >     sun8i_emac_eth_start: Timeout
> >
> > According to the commit message the change of the MDIO frequency is only
> > required for external PHYs.
> >
> > Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency")
> > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> > ---
> >  drivers/net/sun8i_emac.c | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> > index 5a1b38bf80..d7553fe163 100644
> > --- a/drivers/net/sun8i_emac.c
> > +++ b/drivers/net/sun8i_emac.c
> > @@ -211,7 +211,9 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
> >          * The EMAC clock is either 200 or 300 MHz, so we need a divider
> >          * of 128 to get the MDIO frequency below the required 2.5 MHz.
> >          */
> > -       mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
> > +       if (!priv->use_internal_phy)
> > +               mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
> > +                          MDIO_CMD_MII_CLK_CSR_SHIFT;
> >
> >         mii_cmd |= MDIO_CMD_MII_BUSY;
> >
> > @@ -242,7 +244,9 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
> >          * The EMAC clock is either 200 or 300 MHz, so we need a divider
> >          * of 128 to get the MDIO frequency below the required 2.5 MHz.
> >          */
> > -       mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
> > +       if (!priv->use_internal_phy)
> > +               mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
> > +                          MDIO_CMD_MII_CLK_CSR_SHIFT;
> >
> >         mii_cmd |= MDIO_CMD_MII_WRITE;
> >         mii_cmd |= MDIO_CMD_MII_BUSY;
> > --
> > 2.31.0
> >
> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
applied to u-boot-net/master, thanks!

Best regards,
Ramon Fried

      reply	other threads:[~2021-06-12 18:41 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-03  7:52 [PATCH 1/1] net: sun8i-emac: fix MDIO frequency Heinrich Schuchardt
2021-06-10  5:48 ` Ramon Fried
2021-06-12 18:41   ` Ramon Fried [this message]

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