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charset=UTF-8 Date: Sat, 12 Jun 2021 21:41:32 +0300 Message-Id: Cc: "Joe Hershberger" , "U-Boot Mailing List" , "Jagan Teki" , "Andre Przywara" Subject: Re: [PATCH 1/1] net: sun8i-emac: fix MDIO frequency From: "Ramon Fried" To: "Ramon Fried" , "Heinrich Schuchardt" References: <20210603075242.96527-1-xypron.glpk@gmx.de> In-Reply-To: X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Thu Jun 10, 2021 at 8:48 AM IDT, Ramon Fried wrote: > On Thu, Jun 3, 2021 at 10:52 AM Heinrich Schuchardt > wrote: > > > > Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to > > network failure on the OrangePi PC. > > > > =3D> dhcp > > sun8i_emac_eth_start: Timeout > > > > According to the commit message the change of the MDIO frequency is onl= y > > required for external PHYs. > > > > Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") > > Signed-off-by: Heinrich Schuchardt > > --- > > drivers/net/sun8i_emac.c | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c > > index 5a1b38bf80..d7553fe163 100644 > > --- a/drivers/net/sun8i_emac.c > > +++ b/drivers/net/sun8i_emac.c > > @@ -211,7 +211,9 @@ static int sun8i_mdio_read(struct mii_dev *bus, int= addr, int devad, int reg) > > * The EMAC clock is either 200 or 300 MHz, so we need a divide= r > > * of 128 to get the MDIO frequency below the required 2.5 MHz. > > */ > > - mii_cmd |=3D MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_C= SR_SHIFT; > > + if (!priv->use_internal_phy) > > + mii_cmd |=3D MDIO_CMD_MII_CLK_CSR_DIV_128 << > > + MDIO_CMD_MII_CLK_CSR_SHIFT; > > > > mii_cmd |=3D MDIO_CMD_MII_BUSY; > > > > @@ -242,7 +244,9 @@ static int sun8i_mdio_write(struct mii_dev *bus, in= t addr, int devad, int reg, > > * The EMAC clock is either 200 or 300 MHz, so we need a divide= r > > * of 128 to get the MDIO frequency below the required 2.5 MHz. > > */ > > - mii_cmd |=3D MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_C= SR_SHIFT; > > + if (!priv->use_internal_phy) > > + mii_cmd |=3D MDIO_CMD_MII_CLK_CSR_DIV_128 << > > + MDIO_CMD_MII_CLK_CSR_SHIFT; > > > > mii_cmd |=3D MDIO_CMD_MII_WRITE; > > mii_cmd |=3D MDIO_CMD_MII_BUSY; > > -- > > 2.31.0 > > > Reviewed-by: Ramon Fried applied to u-boot-net/master, thanks! Best regards, Ramon Fried