From: Andrew Davis <afd@ti.com>
To: Santhosh Kumar K <s-k6@ti.com>, <trini@konsulko.com>, <nm@ti.com>,
<vigneshr@ti.com>, <bb@ti.com>, <u-kumar1@ti.com>,
<m-chawdhry@ti.com>
Cc: <u-boot@lists.denx.de>, <n-francis@ti.com>
Subject: Re: [PATCH v2 5/8] drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC
Date: Wed, 15 May 2024 11:07:34 -0500 [thread overview]
Message-ID: <e6387a6f-fe4b-4bff-99fd-1418b17aee78@ti.com> (raw)
In-Reply-To: <20240510084707.1903133-6-s-k6@ti.com>
On 5/10/24 3:47 AM, Santhosh Kumar K wrote:
> From: Neha Malcom Francis <n-francis@ti.com>
>
> Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
> only when the config has been enabled.
>
> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
> ---
> drivers/ram/Kconfig | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
> index 9838a2798f92..9d1eee1d5cad 100644
> --- a/drivers/ram/Kconfig
> +++ b/drivers/ram/Kconfig
> @@ -107,6 +107,17 @@ config IMXRT_SDRAM
> to support external memories like sdram, psram & nand.
> This driver is for the sdram memory interface with the SEMC.
>
> +config K3_INLINE_ECC
> + bool "Enable TI Inline ECC support"
> + depends on K3_DDRSS
> + default n
n is already the default, this line is never needed.
Maybe we want this to be `default y` so that we do not change
current behavior and platforms can opt-out as needed instead.
Andrew
> + help
> + Enable Inline ECC support on K3 platforms. 1/9th of the SDRAM space
> + is used for ECC storage and the rest 8/9th is available for system
> + use. Enabling ECC increases boot time as the ECC protected regions
> + need to be primed with a predefined value prior to enabling ECC
> + check.
> +
> source "drivers/ram/aspeed/Kconfig"
> source "drivers/ram/cadence/Kconfig"
> source "drivers/ram/octeon/Kconfig"
next prev parent reply other threads:[~2024-05-15 16:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 8:46 [PATCH v2 0/8] ECC Series Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 1/8] ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 2/8] ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 3/8] ram: k3-ddrss: Setup ECC region start and range Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 4/8] ram: k3-ddrss: Enable ECC interrupts Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 5/8] drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC Santhosh Kumar K
2024-05-15 16:07 ` Andrew Davis [this message]
2024-05-20 2:51 ` Neha Malcom Francis
2024-05-10 8:47 ` [PATCH v2 6/8] configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2 Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 7/8] board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 8/8] arm: dts: k3-*-ddr: Add ss_cfg reg entry Santhosh Kumar K
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