From: Santhosh Kumar K <s-k6@ti.com>
To: <trini@konsulko.com>, <nm@ti.com>, <vigneshr@ti.com>, <bb@ti.com>,
<u-kumar1@ti.com>, <m-chawdhry@ti.com>
Cc: <u-boot@lists.denx.de>, <n-francis@ti.com>, <s-k6@ti.com>
Subject: [PATCH v2 0/8] ECC Series
Date: Fri, 10 May 2024 14:16:59 +0530 [thread overview]
Message-ID: <20240510084707.1903133-1-s-k6@ti.com> (raw)
Hello,
This series is to:
Add support for Inline ECC in DDR for AM64X, AM62X, AM62AX, AM62PX,
J721S2 and J784S4 devices.
(1/8) Enable ECC priming with BIST engine
(2/8) Add a function to store base address and size of RAM's banks
in a 64-bit device private data
(3/8) Setup the ECC region start and range
(4/8) Enable ECC 1-bit error, 2-bit error and multiple-bit
error interrupts
(5/8) Add CONFIG_K3_INLINE_ECC
(6/8) Set NR_DRAM_BANKS to 2
(7/8) Pull Redundant DDR functions to a common location and Fixup
DDR size when ECC is enabled
(8/8) Add ss_cfg reg entry
Changes since v1:
Add support for J7* devices.
v1: https://lore.kernel.org/u-boot/20240131060213.1128024-1-s-k6@ti.com/T/#m19d34d1ebc2802ad80e2412265e7858c98b0510f
Test Results:
https://gist.github.com/santhosh21/53c6f285640c4b6dfb3420d84975d12a
This series contains changes that grab the memory node from the DTS
to set/modify DRAM bank sizes. A kernel patch has been sent [1]
setting the required nodes to be available at bootloader stage. This
patch series can be merged only after the DTS changes have been
reflected in U-Boot either via OF_UPSTREAM (for devices that have
moved to it) or via a sync to U-Boot patch.
[1] https://lore.kernel.org/all/20240506110203.3230255-1-n-francis@ti.com/
Thanks and Regards,
Santhosh.
Georgi Vlaev (1):
ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming
Neha Malcom Francis (2):
drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC
configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2
Santhosh Kumar K (5):
ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve
'calculations restricted to 32 bits' issue
ram: k3-ddrss: Setup ECC region start and range
ram: k3-ddrss: Enable ECC interrupts
board: ti: Pull redundant DDR functions to a common location and Fixup
DDR size when ECC is enabled
arm: dts: k3-*-ddr: Add ss_cfg reg entry
arch/arm/dts/k3-am62a-ddr.dtsi | 7 +-
arch/arm/dts/k3-j721s2-ddr.dtsi | 12 +-
arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++--
board/ti/am62ax/evm.c | 17 +--
board/ti/am62px/evm.c | 18 +--
board/ti/am62x/evm.c | 63 ++--------
board/ti/am64x/evm.c | 73 ++---------
board/ti/am65x/evm.c | 29 +----
board/ti/common/Makefile | 1 +
board/ti/common/k3-ddr-init.c | 89 +++++++++++++
board/ti/common/k3-ddr-init.h | 15 +++
board/ti/j721e/evm.c | 29 +----
board/ti/j721s2/evm.c | 35 ++----
board/ti/j784s4/evm.c | 17 +--
configs/j7200_evm_r5_defconfig | 1 +
configs/j721e_evm_r5_defconfig | 1 +
configs/j721s2_evm_r5_defconfig | 1 +
configs/j784s4_evm_r5_defconfig | 1 +
drivers/ram/Kconfig | 11 ++
drivers/ram/k3-ddrss/k3-ddrss.c | 214 +++++++++++++++++++++++++++-----
20 files changed, 391 insertions(+), 267 deletions(-)
create mode 100644 board/ti/common/k3-ddr-init.c
create mode 100644 board/ti/common/k3-ddr-init.h
--
2.34.1
next reply other threads:[~2024-05-10 8:48 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 8:46 Santhosh Kumar K [this message]
2024-05-10 8:47 ` [PATCH v2 1/8] ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 2/8] ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 3/8] ram: k3-ddrss: Setup ECC region start and range Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 4/8] ram: k3-ddrss: Enable ECC interrupts Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 5/8] drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC Santhosh Kumar K
2024-05-15 16:07 ` Andrew Davis
2024-05-20 2:51 ` Neha Malcom Francis
2024-05-10 8:47 ` [PATCH v2 6/8] configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2 Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 7/8] board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled Santhosh Kumar K
2024-05-10 8:47 ` [PATCH v2 8/8] arm: dts: k3-*-ddr: Add ss_cfg reg entry Santhosh Kumar K
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240510084707.1903133-1-s-k6@ti.com \
--to=s-k6@ti.com \
--cc=bb@ti.com \
--cc=m-chawdhry@ti.com \
--cc=n-francis@ti.com \
--cc=nm@ti.com \
--cc=trini@konsulko.com \
--cc=u-boot@lists.denx.de \
--cc=u-kumar1@ti.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).