From: Michael Walle <mwalle@kernel.org>
To: Jagan Teki <jagan@amarulasolutions.com>,
Andre Przywara <andre.przywara@arm.com>,
Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>, Tom Rini <trini@konsulko.com>,
Joe Hershberger <joe.hershberger@ni.com>,
Ramon Fried <rfried.dev@gmail.com>
Cc: Samuel Holland <samuel@sholland.org>,
u-boot@lists.denx.de, Michael Walle <mwalle@kernel.org>
Subject: [PATCH 0/2] sunxi: v3s: add network support
Date: Mon, 13 May 2024 22:56:07 +0200 [thread overview]
Message-ID: <20240513205609.1872861-1-mwalle@kernel.org> (raw)
Add network support for the V3s which only supports the internal
PHY. Adding support was straight forward. The emac driver just needs
the compatible string and some platform data and the clock driver
needs to know the bits for the clock gating as well as the reset
bits.
This was tested on a custom board.
Michael Walle (2):
clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC
net: sun8i_emac: add support for the V3s
drivers/clk/sunxi/clk_v3s.c | 6 ++++++
drivers/net/sun8i_emac.c | 7 +++++++
2 files changed, 13 insertions(+)
--
2.39.2
next reply other threads:[~2024-05-13 20:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-13 20:56 Michael Walle [this message]
2024-05-13 20:56 ` [PATCH 1/2] clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC Michael Walle
2024-05-14 10:16 ` Andre Przywara
2024-05-13 20:56 ` [PATCH 2/2] net: sun8i_emac: add support for the V3s Michael Walle
2024-05-14 10:27 ` Andre Przywara
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