messages from 2021-07-12 05:41:25 to 2021-08-17 21:18:26 UTC [more...]
[PATCH v2 00/21] target/riscv: Use tcg_constant_*
2021-08-17 21:17 UTC (9+ messages)
` [PATCH v2 01/21] "
` [PATCH v2 02/21] target/riscv: Clean up division helpers
` [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
` [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers
` [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith*
` [PATCH v2 06/21] target/riscv: Remove gen_arith_div*
` [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu
` [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM
[PATCH v2] hw/intc/sifive_clint: Fix overflow in sifive_clint_write_timecmp()
2021-08-17 7:59 UTC (3+ messages)
[PATCH RFC v6 00/12] Add riscv kvm accel support
2021-08-17 3:24 UTC (13+ messages)
` [PATCH RFC v6 01/12] linux-header: Update linux/kvm.h
` [PATCH RFC v6 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
` [PATCH RFC v6 03/12] target/riscv: Implement function kvm_arch_init_vcpu
` [PATCH RFC v6 04/12] target/riscv: Implement kvm_arch_get_registers
` [PATCH RFC v6 05/12] target/riscv: Implement kvm_arch_put_registers
` [PATCH RFC v6 06/12] target/riscv: Support start kernel directly by KVM
` [PATCH RFC v6 07/12] target/riscv: Support setting external interrupt "
` [PATCH RFC v6 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
` [PATCH RFC v6 09/12] target/riscv: Add host cpu type
` [PATCH RFC v6 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
` [PATCH RFC v6 11/12] target/riscv: Implement virtual time adjusting with vm state changing
` [PATCH RFC v6 12/12] target/riscv: Support virtual time context synchronization
[PATCH] hw/intc/sifive_clint: Fix overflow in sifive_clint_write_timecmp()
2021-08-16 17:30 UTC
[PATCH] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()
2021-08-13 9:19 UTC (5+ messages)
[RFC PATCH v4 0/4] Add basic support for custom CSR
2021-08-13 5:33 UTC (17+ messages)
` [RFC PATCH v4 1/4] Add options to config/meson files "
` [RFC PATCH v4 2/4] Adding basic custom/vendor CSR handling mechanism
` [RFC PATCH v4 3/4] Adding Andes AX25 and A25 CPU model
` [RFC PATCH v4 4/4] Enable custom CSR logic for Andes AX25 and A25
[PATCH v2 1/1] target/riscv: Add User CSRs read-only check
2021-08-13 1:42 UTC (2+ messages)
[PATCH v2] target/riscv: Don't wrongly override isa version
2021-08-13 0:52 UTC (3+ messages)
[RFC PATCH 00/13] Support UXL field in mstatus
2021-08-12 7:20 UTC (41+ messages)
` [RFC PATCH 01/13] target/riscv: Add UXL to tb flags
` [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions
` [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store
` [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu
` [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction
` [RFC PATCH 06/13] target/riscv: Fix div instructions
` [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM
` [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions
` [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions
` [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions
` [RFC PATCH 11/13] target/riscv: Fix srow
` [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB
` [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR
[PATCH] target/riscv: Don't wrongly overide isa version
2021-08-11 14:18 UTC (4+ messages)
[PATCH 0/2] Set user creatable for flag ibex uart and plic
2021-08-11 11:48 UTC (5+ messages)
` [PATCH 1/2] hw/char/ibex_uart: set user-creatable
` [PATCH 2/2] hw/char/ibex_plic: "
[PATCH for-6.2 04/12] [automated] Add struct names to typedefs used by QOM types
2021-08-10 13:06 UTC (14+ messages)
` [PATCH for-6.2 05/12] [automated] Move QOM typedefs and add missing includes
` [PATCH for-6.2 06/12] [automated] Split QOM "typedef struct T { ... } T" declarations
` [PATCH for-6.2 07/12] [automated] Use DECLARE_*CHECKER* macros when possible
` [PATCH for-6.2 12/12] [automated] Use OBJECT_DECLARE_SIMPLE_TYPE "
[PATCH] target/riscv: Add User CSRs read-only check
2021-08-09 10:39 UTC (2+ messages)
[PATCH] target/riscv: Add User CSRs read-only check
2021-08-09 9:49 UTC (4+ messages)
[PATCH] target/riscv: Correct a comment in riscv_csrrw()
2021-08-09 1:04 UTC (3+ messages)
[PATCH] hw/riscv: virt: Move flash node to root
2021-08-09 1:03 UTC (4+ messages)
[PATCH v2 0/4] QEMU RISC-V ACLINT Support
2021-08-06 2:30 UTC (13+ messages)
` [PATCH v2 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources
` [PATCH v2 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
` [PATCH v2 3/4] hw/riscv: virt: Re-factor FDT generation
` [PATCH v2 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine
[PATCH] hw/char: Add config for shakti uart
2021-08-01 23:31 UTC (3+ messages)
[PATCH for-6.2 09/43] target/riscv: Implement do_unaligned_access for user-only
2021-07-30 6:13 UTC (2+ messages)
[PATCH v2 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
2021-07-23 6:49 UTC (12+ messages)
` [PATCH v2 2/5] hw/intc: sifive_clint: Use RISC-V CPU "
` [PATCH v2 3/5] hw/intc: ibex_plic: Convert the PLIC to use "
` [PATCH v2 4/5] hw/intc: sifive_plic: "
` [PATCH v2 5/5] hw/intc: ibex_timer: Convert the timer "
[PATCH 00/17] target/riscv: Use tcg_constant_*
2021-07-23 5:02 UTC (35+ messages)
` [PATCH 03/17] target/riscv: Use gpr_{src,dst} in shift operations
` [PATCH 03/17] target/riscv: Use gpr_{src, dst} "
` [PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations
` [PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi
` [PATCH 06/17] target/riscv: Use gpr_src in branches
` [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store
` [PATCH 07/17] target/riscv: Use gpr_{src, dst} "
` [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations
` [PATCH 09/17] target/riscv: Reorg csr instructions
` [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA
` [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB
` [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF
` [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD
` [PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc
` [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu
` [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV
` [PATCH 17/17] target/riscv: Remove gen_get_gpr
[PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines
2021-07-22 12:15 UTC (8+ messages)
` [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU "
` [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use "
Re:[PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst
2021-07-20 3:37 UTC
[PATCH v2 1/1] hw/riscv/boot: Check the error of fdt_pack()
2021-07-15 6:58 UTC (2+ messages)
[PATCH v1 1/1] hw/riscv/boot: Check the error of fdt_pack()
2021-07-15 6:57 UTC (4+ messages)
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-07-13 7:15 UTC (6+ messages)
` [RFC PATCH 03/11] hw/intc: Add CLIC device
` [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode
[PATCH v1 0/3] RISC-V ACLINT Support
2021-07-12 23:05 UTC (12+ messages)
` [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation
` [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
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