messages from 2021-05-17 10:53:23 to 2021-06-12 16:07:00 UTC [more...]
[PATCH v1 0/3] RISC-V ACLINT Support
2021-06-12 16:06 UTC (4+ messages)
` [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
` [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation
` [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
[PATCH 0/4] AIA local interrupt CSR support
2021-06-11 14:04 UTC (15+ messages)
` [PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs
` [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs
` [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
` [PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available
[PATCH v2 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer
2021-06-11 11:52 UTC (10+ messages)
` [PATCH v2 1/3] hw/char/ibex_uart: Make the register layout private
` [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
` [PATCH v2 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-06-11 9:26 UTC (8+ messages)
` [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode
[PATCH v2 00/37] target/riscv: support packed extension v0.9.4
2021-06-11 4:36 UTC (42+ messages)
` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters
` [PATCH v2 02/37] target/riscv: Make the vector helper functions public
` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions
` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions
` [PATCH v2 06/37] target/riscv: SIMD 8-bit "
` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions
` [PATCH v2 08/37] target/riscv: SIMD 8-bit "
` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions
` [PATCH v2 10/37] target/riscv: SIMD 8-bit "
` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions
` [PATCH v2 12/37] target/riscv: SIMD 8-bit "
` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions
` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions
` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions
` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 "
` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit "
` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions
` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions
` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions
` [PATCH v2 22/37] target/riscv: 32-bit Multiply "
` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with "
` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions
` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 "
` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions
` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions
` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit "
` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel "
` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions
` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line
TCG op for 32 bit only cpu on qemu-riscv64
2021-06-11 2:33 UTC (8+ messages)
[RFC PATCH v3 0/2] Proposing custom CSR handling logic
2021-06-10 23:22 UTC (7+ messages)
` [RFC PATCH v3 1/2] Adding Andes AX25 CPU model
` [RFC PATCH v3 2/2] Adding preliminary custom/vendor CSR handling mechanism
[PATCH 0/2] target/riscv: fix hypervisor exceptions
2021-06-10 23:14 UTC (5+ messages)
` [PATCH 1/2] target/riscv: fix VS interrupts forwarding to HS
` [PATCH 2/2] target/riscv: remove force HS exception
[PATCH] target/riscv: hardwire bits in hideleg and hedeleg
2021-06-10 23:12 UTC (6+ messages)
[PATCH v1 1/1] target/riscv: Use target_ulong for the DisasContext misa
2021-06-10 23:02 UTC (3+ messages)
[PATCH v9 0/6] RISC-V Pointer Masking implementation
2021-06-10 22:46 UTC (8+ messages)
` [PATCH v9 1/6] [RISCV_PM] Add J-extension into RISC-V
` [PATCH v9 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v9 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
` [PATCH v9 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v9 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v9 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
[PATCH v16 13/99] meson: add target_user_arch
2021-06-05 22:33 UTC (4+ messages)
` [PATCH v16 93/99] meson: Introduce target-specific Kconfig
[PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
2021-06-05 18:59 UTC (3+ messages)
[PATCH v1 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer
2021-06-04 2:41 UTC (14+ messages)
` [PATCH v1 1/3] hw/char/ibex_uart: Make the register layout private
` [PATCH v1 2/3] hw/timer: Initial commit of Ibex Timer
` [PATCH v1 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
[PATCH v2 00/12] hw: Various Kconfig fixes
2021-06-03 16:40 UTC (7+ messages)
` [PATCH v2 02/12] hw/ide/Kconfig: Add missing dependency PCI -> IDE_QDEV
[PATCH v3] target/riscv: fix VS interrupts forwarding to HS
2021-06-02 19:14 UTC (7+ messages)
HSS Issue with GCC 10, Qemu Setup for microchip-icicle-kit
2021-06-01 18:36 UTC (10+ messages)
[PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
2021-06-01 6:41 UTC (3+ messages)
[PATCH v2 0/2] QOMify Sifive UART Model
2021-05-31 8:13 UTC (7+ messages)
` [PATCH v2 1/2] hw/char: sifive_uart
` [PATCH v2 2/2] "
[PATCH 1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode
2021-05-28 0:32 UTC (3+ messages)
[PATCH v6 00/17] support subsets of bitmanip extension
2021-05-27 22:08 UTC (6+ messages)
` [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
` [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option
[PATCH v7 00/23] cpu: Introduce SysemuCPUOps structure
2021-05-26 17:47 UTC (19+ messages)
` [PATCH v7 02/23] cpu: Restrict target cpu_do_transaction_failed() handlers to sysemu
` [PATCH v7 04/23] cpu: Remove duplicated 'sysemu/hw_accel.h' header
` [PATCH v7 05/23] cpu: Split as cpu-common / cpu-sysemu
` [PATCH v7 13/23] cpu: Move AVR target vmsd field from CPUClass to DeviceClass
` [PATCH v7 18/23] cpu: Move CPUClass::write_elf* to SysemuCPUOps
` [PATCH v7 19/23] cpu: Move CPUClass::asidx_from_attrs "
` [PATCH v7 20/23] cpu: Move CPUClass::get_phys_page_debug "
` [PATCH v7 21/23] cpu: Move CPUClass::get_memory_mapping "
` [PATCH v7 22/23] cpu: Move CPUClass::get_paging_enabled "
` [PATCH v7 23/23] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
[PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction
2021-05-26 6:15 UTC (4+ messages)
[PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions
2021-05-26 5:31 UTC (3+ messages)
[PATCH] target/riscv: Pass the same value to oprsz and maxsz
2021-05-25 22:01 UTC (3+ messages)
[PATCH v1 1/1] target/riscv/pmp: Add assert for ePMP operations
2021-05-25 21:53 UTC (4+ messages)
[PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions
2021-05-24 4:46 UTC (2+ messages)
[PATCH v2] target/riscv: Dump CSR mscratch/sscratch/satp
2021-05-20 7:20 UTC (2+ messages)
[PATCH] target/riscv: Remove unnecessary riscv_*_names[] declaration
2021-05-20 7:15 UTC (2+ messages)
[PATCH] target/riscv: Remove obsolete 'CPU unmigratable' comment
2021-05-18 6:11 UTC (5+ messages)
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).