messages from 2021-04-24 17:14:29 to 2021-05-17 10:53:23 UTC [more...]
[PATCH v7 00/23] cpu: Introduce SysemuCPUOps structure
2021-05-17 10:51 UTC (19+ messages)
` [PATCH v7 01/23] NOTFORMERGE target/arm: Restrict MTE code to softmmu
` [PATCH v7 02/23] cpu: Restrict target cpu_do_transaction_failed() handlers to sysemu
` [PATCH v7 03/23] cpu: Restrict target cpu_do_unaligned_access() "
` [PATCH v7 04/23] cpu: Remove duplicated 'sysemu/hw_accel.h' header
` [PATCH v7 05/23] cpu: Split as cpu-common / cpu-sysemu
` [PATCH v7 06/23] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
` [PATCH v7 07/23] cpu: Introduce cpu_virtio_is_big_endian()
` [PATCH v7 08/23] cpu: Directly use cpu_write_elf*() fallback handlers in place
` [PATCH v7 09/23] cpu: Directly use get_paging_enabled() "
` [PATCH v7 10/23] cpu: Directly use get_memory_mapping() "
` [PATCH v7 11/23] cpu: Assert DeviceClass::vmsd is NULL on user emulation
` [PATCH v7 12/23] cpu: Rename CPUClass vmsd -> legacy_vmsd
` [PATCH v7 13/23] cpu: Move AVR target vmsd field from CPUClass to DeviceClass
` [PATCH v7 14/23] cpu: Introduce SysemuCPUOps structure
` [PATCH v7 15/23] cpu: Move CPUClass::vmsd to SysemuCPUOps
` [PATCH v7 16/23] cpu: Move CPUClass::virtio_is_big_endian "
` [PATCH v7 17/23] cpu: Move CPUClass::get_crash_info "
` [PATCH v7 19/23] cpu: Move CPUClass::asidx_from_attrs "
[PATCH] target/riscv: Remove obsolete 'CPU unmigratable' comment
2021-05-17 7:08 UTC
[PATCH v6 00/18] cpu: Introduce SysemuCPUOps structure
2021-05-17 5:27 UTC (7+ messages)
` [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
` [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
[PATCH v2 00/12] hw: Various Kconfig fixes
2021-05-17 5:10 UTC (29+ messages)
` [PATCH v2 01/12] hw/mem/nvdimm: Use Kconfig 'imply' instead of 'depends on'
` [PATCH v2 02/12] hw/ide/Kconfig: Add missing dependency PCI -> IDE_QDEV
` [PATCH v2 03/12] hw/arm/Kconfig: Add missing dependency NPCM7XX -> SMBUS
` [PATCH v2 04/12] hw/arm/Kconfig: Remove unused DS1338 symbol from i.MX25 PDK Board
` [PATCH v2 05/12] hw/arm/Kconfig: Add missing SDHCI symbol to FSL_IMX25
` [PATCH v2 06/12] hw/riscv/Kconfig: Add missing dependency MICROCHIP_PFSOC -> SERIAL
` [PATCH v2 07/12] hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines
` [PATCH v2 08/12] hw/ppc/Kconfig: Add missing dependency E500 -> DS1338 RTC
` [PATCH v2 09/12] hw/pci-host/Kconfig: Add missing dependency MV64361 -> I8259
` [PATCH v2 10/12] hw/isa/vt82c686: Add missing Kconfig dependencies (build error)
` [PATCH v2 11/12] hw/isa/vt82c686: Add missing Kconfig dependency (runtime error)
` [PATCH v2 12/12] hw/ppc/Kconfig: Add dependency PEGASOS2 -> ATI_VGA
[PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
2021-05-17 1:42 UTC (4+ messages)
[PATCH] target/riscv: Remove unnecessary riscv_*_names[] declaration
2021-05-16 23:13 UTC (3+ messages)
[PATCH 0/2] QOMify Sifive UART model
2021-05-16 11:13 UTC (9+ messages)
` [PATCH 1/2] Consistent function names for sifive uart read and write function
` [PATCH 2/2] QOMify sifive_uart model
[PATCH 0/4] AIA local interrupt CSR support
2021-05-14 14:32 UTC (5+ messages)
` [PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs
` [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs
` [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
` [PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available
[PATCH 06/10] hw/riscv/Kconfig: Add missing dependency MICROCHIP_PFSOC -> SERIAL
2021-05-14 8:14 UTC (5+ messages)
` [PATCH 07/10] hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines
[PATCH] target/riscv: Dump CSR mscratch/sscratch/satp
2021-05-14 3:18 UTC (3+ messages)
[PATCH v2] target/riscv: fix VS interrupts forwarding to HS
2021-05-13 0:17 UTC (2+ messages)
[PATCH V2 0/2] Proposing custom CSR handling logic
2021-05-12 23:41 UTC (8+ messages)
` [PATCH V2 1/2] Adding premliminary support for custom CSR handling mechanism
` [PATCH V2 2/2] Adding custom Andes CSR table
[PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
2021-05-12 5:59 UTC (9+ messages)
` [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
` [PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
` [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
[PATCH 0/1] Proposing custom CSR handling logic
2021-05-11 6:07 UTC (2+ messages)
` [PATCH 1/1] Adding premliminary support for custom CSR handling mechanism
[RFC PATCH 0/5] RISC-V:support Nuclei FPGA Evaluation Kit
2021-05-11 4:03 UTC (16+ messages)
` [RFC PATCH 1/5] target/riscv: Add Nuclei CSR and Update interrupt handling
` [RFC PATCH 2/5] hw/intc: Add Nuclei ECLIC device
` [RFC PATCH 3/5] hw/intc: Add Nuclei Systimer
` [RFC PATCH 4/5] hw/char: Add Nuclei Uart
` [RFC PATCH 5/5] Nuclei FPGA Evaluation Kit MCU Machine
[PATCH v6 00/17] support subsets of bitmanip extension
2021-05-10 7:26 UTC (22+ messages)
` [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension
` [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros
` [PATCH v6 03/17] target/riscv: rvb: count bits set
` [PATCH v6 04/17] target/riscv: rvb: logic-with-negate
` [PATCH v6 05/17] target/riscv: rvb: pack two words into one register
` [PATCH v6 06/17] target/riscv: rvb: min/max instructions
` [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions
` [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
` [PATCH v6 09/17] target/riscv: rvb: single-bit instructions
` [PATCH v6 10/17] target/riscv: rvb: shift ones
` [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
` [PATCH v6 12/17] target/riscv: rvb: generalized reverse
` [PATCH v6 13/17] target/riscv: rvb: generalized or-combine
` [PATCH v6 14/17] target/riscv: rvb: address calculation
` [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend
` [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line
` [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option
target.xml
2021-05-07 12:02 UTC
[PATCH RFC v5 00/12] Add riscv kvm accel support
2021-05-06 7:59 UTC (4+ messages)
` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
[PATCH v2] target/riscv: fix wfi exception behavior
2021-05-06 2:09 UTC (3+ messages)
[PATCH] docs/system: riscv: Include shakti_c machine documentation
2021-05-05 23:00 UTC (3+ messages)
[PATCH v1 1/1] docs/system: Move the RISC-V -bios information to removed
2021-05-04 3:12 UTC (2+ messages)
[PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
2021-05-03 3:00 UTC (9+ messages)
` [PATCH v2 2/8] hw/riscv: virt: "
` [PATCH v2 3/8] hw/riscv: Support the official CLINT DT bindings
` [PATCH v2 4/8] hw/riscv: Support the official PLIC "
` [PATCH v2 5/8] docs/system/riscv: Correct the indentation level of supported devices
` [PATCH v2 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage
` [PATCH v2 7/8] hw/riscv: Use macros for BIOS image names
` [PATCH v2 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot
[PATCH 0/7] hw/nvram/fw_cfg: Do not build device if not needed (Spring cleanup)
2021-04-28 18:50 UTC (18+ messages)
` [PATCH 1/7] stubs: Restrict fw_cfg stubs to sysemu
` [PATCH 2/7] hw/nvram: Rename FW_CFG_MIPS as generic FW_CFG Kconfig symbol
` [PATCH 3/7] hw/nvram: Declare FW_CFG_DMA Kconfig symbol in hw/nvram/
` [PATCH 4/7] hw/acpi/vmgenid: Make ACPI_VMGENID depends on FW_CFG Kconfig
` [PATCH 5/7] hw: Have machines Kconfig-select FW_CFG
` [PATCH 6/7] hw/{arm,hppa,riscv}: Add fw_cfg arch-specific stub
` [PATCH 7/7] hw/nvram: Do not build FW_CFG if not required
[PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
2021-04-28 4:07 UTC
[PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
2021-04-28 3:55 UTC
[PATCH v8 0/6] RISC-V Pointer Masking implementation
2021-04-27 22:18 UTC (8+ messages)
` [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
` [PATCH v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
` [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
[PATCH v5 00/17] support subsets of bitmanip extension
2021-04-27 7:13 UTC (14+ messages)
` [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros
` [PATCH v5 03/17] target/riscv: rvb: count bits set
` [PATCH v5 04/17] target/riscv: rvb: logic-with-negate
` [PATCH v5 05/17] target/riscv: rvb: pack two words into one register
` [PATCH v5 06/17] target/riscv: rvb: min/max instructions
` [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions
[PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
2021-04-26 5:33 UTC (10+ messages)
` [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
` [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
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