messages from 2021-04-09 12:23:21 to 2021-04-24 17:14:29 UTC [more...]
[PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
2021-04-24 17:14 UTC (13+ messages)
` [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro
` [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro
` [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro
` [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro
` [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro
` [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro
` [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro
` [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
` [PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions
` [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
[PATCH v6 00/18] cpu: Introduce SysemuCPUOps structure
2021-04-23 1:24 UTC (23+ messages)
` [PATCH v6 01/18] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
` [PATCH v6 02/18] cpu: Introduce cpu_virtio_is_big_endian()
` [PATCH v6 03/18] cpu: Directly use cpu_write_elf*() fallback handlers in place
` [PATCH v6 04/18] cpu: Directly use get_paging_enabled() "
` [PATCH v6 05/18] cpu: Directly use get_memory_mapping() "
` [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
` [PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd
` [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
` [PATCH v6 09/18] cpu: Introduce SysemuCPUOps structure
` [PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps
` [PATCH v6 11/18] cpu: Move CPUClass::virtio_is_big_endian "
` [PATCH v6 12/18] cpu: Move CPUClass::get_crash_info "
` [PATCH v6 13/18] cpu: Move CPUClass::write_elf* "
` [PATCH v6 14/18] cpu: Move CPUClass::asidx_from_attrs "
` [PATCH v6 15/18] cpu: Move CPUClass::get_phys_page_debug "
` [PATCH v6 16/18] cpu: Move CPUClass::get_memory_mapping "
` [PATCH v6 17/18] cpu: Move CPUClass::get_paging_enabled "
` [PATCH v6 18/18] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
[PATCH v3 00/27] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode
2021-04-22 16:05 UTC (9+ messages)
` [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
[PATCH v5 00/15] cpu: Introduce SysemuCPUOps structure
2021-04-22 11:04 UTC (17+ messages)
` [PATCH v5 01/15] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
` [PATCH v5 02/15] cpu: Introduce cpu_virtio_is_big_endian()
` [PATCH v5 03/15] cpu: Directly use cpu_write_elf*() fallback handlers in place
` [PATCH v5 04/15] cpu: Directly use get_paging_enabled() "
` [PATCH v5 05/15] cpu: Directly use get_memory_mapping() "
` [PATCH v5 06/15] cpu: Introduce SysemuCPUOps structure
` [PATCH v5 07/15] cpu: Move CPUClass::vmsd to SysemuCPUOps
` [PATCH v5 08/15] cpu: Move CPUClass::virtio_is_big_endian "
` [PATCH v5 09/15] cpu: Move CPUClass::get_crash_info "
` [PATCH v5 10/15] cpu: Move CPUClass::write_elf* "
` [PATCH v5 11/15] cpu: Move CPUClass::asidx_from_attrs "
` [PATCH v5 12/15] cpu: Move CPUClass::get_phys_page_debug "
` [PATCH v5 13/15] cpu: Move CPUClass::get_memory_mapping "
` [PATCH v5 14/15] cpu: Move CPUClass::get_paging_enabled "
` [PATCH v5 15/15] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
[PATCH v2 0/9] RISC-V: Steps towards running 32-bit guests on
2021-04-22 2:01 UTC (21+ messages)
` [PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro
` [PATCH v2 2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro
` [PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro
` [PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro
` [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro
` [PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro
` [PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro
` [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions
` [PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions
[PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-22 1:42 UTC (5+ messages)
[PATCH] target/riscv: fix a typo with interrupt names
2021-04-22 0:24 UTC (2+ messages)
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-04-22 0:21 UTC (13+ messages)
` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
` [RFC PATCH 03/11] hw/intc: Add CLIC device
[RFC] target/riscv: generated RISCV isa string and subset naming convention
2021-04-21 14:18 UTC
[PATCH v5 00/17] support subsets of bitmanip extension
2021-04-21 4:13 UTC (18+ messages)
` [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension
` [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros
` [PATCH v5 03/17] target/riscv: rvb: count bits set
` [PATCH v5 04/17] target/riscv: rvb: logic-with-negate
` [PATCH v5 05/17] target/riscv: rvb: pack two words into one register
` [PATCH v5 06/17] target/riscv: rvb: min/max instructions
` [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions
` [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
` [PATCH v5 09/17] target/riscv: rvb: single-bit instructions
` [PATCH v5 10/17] target/riscv: rvb: shift ones
` [PATCH v5 11/17] target/riscv: rvb: rotate (left/right)
` [PATCH v5 12/17] target/riscv: rvb: generalized reverse
` [PATCH v5 13/17] target/riscv: rvb: generalized or-combine
` [PATCH v5 14/17] target/riscv: rvb: address calculation
` [PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend
` [PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line
` [PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option
[PATCH v2] target/riscv: fix wfi exception behavior
2021-04-20 21:36 UTC
[PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
2021-04-20 12:39 UTC (8+ messages)
[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-20 1:18 UTC (3+ messages)
[PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-19 23:13 UTC (11+ messages)
` [PATCH v4 1/8] target/riscv: Fix the PMP is locked check when using TOR
` [PATCH v4 2/8] target/riscv: Define ePMP mseccfg
` [PATCH v4 3/8] target/riscv: Add the ePMP feature
` [PATCH v4 4/8] target/riscv: Add ePMP CSR access functions
` [PATCH v4 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v4 6/8] target/riscv: Add a config option for ePMP
` [PATCH v4 7/8] target/riscv/pmp: Remove outdated comment
` [PATCH v4 8/8] target/riscv: Add ePMP support for the Ibex CPU
[PATCH] hw/riscv: Fix OT IBEX reset vector
2021-04-19 21:36 UTC (2+ messages)
[PATCH] target/riscv: fix vrgather macro index variable type bug
2021-04-19 15:30 UTC (2+ messages)
[PATCH] target/riscv: fix vssub.vv saturation bug
2021-04-19 8:49 UTC (4+ messages)
[PATCH] target/riscv: fix wfi exception behavior
2021-04-16 11:34 UTC (3+ messages)
[PATCH] docs: Add documentation for shakti_c machine
2021-04-15 22:33 UTC (3+ messages)
(no subject)
2021-04-15 22:27 UTC (3+ messages)
`
[PATCH 00/38] target/riscv: support packed extension v0.9.2
2021-04-15 5:50 UTC (4+ messages)
[PATCH v3 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-15 4:17 UTC (11+ messages)
` [PATCH v3 1/8] target/riscv: Fix the PMP is locked check when using TOR
` [PATCH v3 2/8] target/riscv: Define ePMP mseccfg
` [PATCH v3 3/8] target/riscv: Add the ePMP feature
` [PATCH v3 4/8] target/riscv: Add ePMP CSR access functions
` [PATCH v3 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v3 6/8] target/riscv: Add a config option for ePMP
` [PATCH v3 7/8] target/riscv/pmp: Remove outdated comment
` [PATCH v3 8/8] target/riscv: Add ePMP support for the Ibex CPU
[PATCH RFC v5 00/12] Add riscv kvm accel support
2021-04-14 22:50 UTC (19+ messages)
` [PATCH RFC v5 01/12] linux-header: Update linux/kvm.h
` [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
` [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu
` [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers
` [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers
` [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM
` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
` [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
` [PATCH RFC v5 09/12] target/riscv: Add host cpu type
` [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
` [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing
` [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization
[PATCH] target/riscv: fix exception index on instruction access fault
2021-04-14 3:42 UTC (2+ messages)
Fix exception index on instruction access fault
2021-04-13 16:20 UTC
[PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on
2021-04-12 9:10 UTC (9+ messages)
` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro
` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro
` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro
` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro
[PATCH v1 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-11 23:03 UTC (4+ messages)
` [PATCH v1 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
[PATCH v2 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-11 4:06 UTC (5+ messages)
` [PATCH v2 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v2 7/8] target/riscv/pmp: Remove outdated comment
medeleg[11] should be hardwired to zero?
2021-04-09 20:15 UTC
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