From: "Fea.Wang" <fea.wang@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: "Fea.Wang" <fea.wang@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
Date: Wed, 15 May 2024 16:06:01 +0800 [thread overview]
Message-ID: <20240515080605.2675399-5-fea.wang@sifive.com> (raw)
In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com>
Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH
and HEDELEGH for exception codes 32-47 for reserving and exception codes
48-63 for custom use. Add the CSR number though the implementation is
just reading zero and writing ignore. Besides, for accessing HEDELEGH, it
should be controlled by mstateen0 'P1P13' bit.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu_bits.h | 2 ++
target/riscv/csr.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 28bd3fb0b4..f888025c59 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -156,6 +156,8 @@
/* 32-bit only */
#define CSR_MSTATUSH 0x310
+#define CSR_MEDELEGH 0x312
+#define CSR_HEDELEGH 0x612
/* Machine Trap Handling */
#define CSR_MSCRATCH 0x340
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index bdbc8de0e2..c5ff40eed8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3225,6 +3225,33 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_hedelegh(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ RISCVException ret;
+ ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ /* Reserved, now read zero */
+ *val = 0;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_hedelegh(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ RISCVException ret;
+ ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ /* Reserved, now write ignore */
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException rmw_hvien64(CPURISCVState *env, int csrno,
uint64_t *ret_val,
uint64_t new_val, uint64_t wr_mask)
@@ -4672,6 +4699,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
write_mstatush },
+ [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore,
+ .min_priv_ver = PRIV_VERSION_1_13_0 },
+ [CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh, write_hedelegh,
+ .min_priv_ver = PRIV_VERSION_1_13_0 },
/* Machine Trap Handling */
[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch,
--
2.34.1
next prev parent reply other threads:[~2024-05-15 8:02 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 8:05 [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec Fea.Wang
2024-05-15 8:05 ` [RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec Fea.Wang
2024-05-15 8:05 ` [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13 Fea.Wang
2024-05-15 8:06 ` [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 Fea.Wang
2024-05-21 6:49 ` LIU Zhiwei
2024-05-15 8:06 ` Fea.Wang [this message]
2024-05-15 8:06 ` [RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err Fea.Wang
2024-05-27 9:21 ` [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec Daniel Henrique Barboza
2024-05-30 3:30 ` Fea Wang
2024-05-30 9:21 ` Daniel Henrique Barboza
2024-05-30 10:37 ` Andrew Jones
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