From: "Fea.Wang" <fea.wang@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: "Fea.Wang" <fea.wang@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
Weiwei Li <liwei1518@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0
Date: Wed, 15 May 2024 16:06:00 +0800 [thread overview]
Message-ID: <20240515080605.2675399-4-fea.wang@sifive.com> (raw)
In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com>
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
SMSTATEEN0 that controls access to the hedeleg.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liwei1518@gmail.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 74318a925c..28bd3fb0b4 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -315,6 +315,7 @@
#define SMSTATEEN0_CS (1ULL << 0)
#define SMSTATEEN0_FCSR (1ULL << 1)
#define SMSTATEEN0_JVT (1ULL << 2)
+#define SMSTATEEN0_P1P13 (1ULL << 56)
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
#define SMSTATEEN0_IMSIC (1ULL << 58)
#define SMSTATEEN0_AIA (1ULL << 59)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6b460ee0e8..bdbc8de0e2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2248,6 +2248,10 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
wr_mask |= SMSTATEEN0_FCSR;
}
+ if (env->priv_ver >= PRIV_VERSION_1_13_0) {
+ wr_mask |= SMSTATEEN0_P1P13;
+ }
+
return write_mstateen(env, csrno, wr_mask, new_val);
}
@@ -2283,6 +2287,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (env->priv_ver >= PRIV_VERSION_1_13_0) {
+ wr_mask |= SMSTATEEN0_P1P13;
+ }
+
return write_mstateenh(env, csrno, wr_mask, new_val);
}
--
2.34.1
next prev parent reply other threads:[~2024-05-15 8:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 8:05 [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec Fea.Wang
2024-05-15 8:05 ` [RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec Fea.Wang
2024-06-04 0:30 ` Alistair Francis
2024-05-15 8:05 ` [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13 Fea.Wang
2024-06-04 0:46 ` Alistair Francis
2024-06-04 0:56 ` Alistair Francis
2024-06-04 3:39 ` Fea Wang
2024-05-15 8:06 ` Fea.Wang [this message]
2024-05-21 6:49 ` [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 LIU Zhiwei
2024-06-04 0:54 ` Alistair Francis
2024-06-04 3:56 ` Fea Wang
2024-05-15 8:06 ` [RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 Fea.Wang
2024-06-04 0:53 ` Alistair Francis
2024-05-15 8:06 ` [RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err Fea.Wang
2024-06-04 0:54 ` Alistair Francis
2024-05-27 9:21 ` [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec Daniel Henrique Barboza
2024-05-30 3:30 ` Fea Wang
2024-05-30 9:21 ` Daniel Henrique Barboza
2024-05-30 10:37 ` Andrew Jones
2024-06-03 6:37 ` Fea Wang
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