From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
ajones@ventanamicro.com, kraxel@redhat.com
Subject: Re: [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU
Date: Wed, 8 May 2024 09:41:18 -0300 [thread overview]
Message-ID: <d8fcb94e-86cf-4497-b450-1a32e4606512@ventanamicro.com> (raw)
In-Reply-To: <CAFEAcA_gu40QoTXUPP2f=8vGvEOTbGWKtqR3b-e7YYhbFG0aiw@mail.gmail.com>
On 5/7/24 12:44, Peter Maydell wrote:
> On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
>>
>> Hi,
>>
>> In this RFC I want to check with Gerd and others if it's ok to add a PCI
>> id for the RISC-V IOMMU device. It's currently under review in [1]. The
>> idea is to fold this patch into the RISC-V IOMMU series if we're all ok
>> with this change.
>
> My question here would be "why is this risc-v specific?" (and more
> generally "what is this for?" -- the cover letter and patch and
> documentation page provide almost no information about what this
> device is and why it needs to exist rather than using either
> virtio-iommu or else a model of a real hardware IOMMU.)
The RISC-V IOMMU device emulation under review ([1]) is a reference implementation of
the riscv-iommu spec [2]. AFAIK it is similar to what we already have with aarch64 'smmuv3'
'virt' bus, i.e. an impl of ARM's SMMUv3 that isn't tied to a specific vendor.
The difference here is that the riscv-iommu spec, ratified by RISC-V International (RVI),
predicts that the device could be implemented as a PCIe device. But RVI didn't bother
assigning a PCI ID for their reference IOMMU. The existing implementation in [1] is using
a Rivos PCI ID that we're treating as a placeholder only. We need an ID that reflects that
this is a device that adheres to the riscv-iommu spec, not to an IOMMU of any particular
vendor.
Since RVI doesn't provide a PCI ID for it we went to Red Hat, and they were kind enough
to give us a PCI ID for the RISC-V IOMMU reference device.
I'll do a proper job this time and add all this context in the commit msg. Including a
proper shout-out to Gerd and Red Hat.
Thanks,
Daniel
[1] https://lore.kernel.org/qemu-riscv/20240307160319.675044-1-dbarboza@ventanamicro.com/
[2] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0
>
> thanks
> -- PMM
next prev parent reply other threads:[~2024-05-08 12:41 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-03 12:42 [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU Daniel Henrique Barboza
2024-05-03 12:42 ` [RFC PATCH 1/1] pci-ids.rst: add Red Hat pci-id for generic IOMMU device Daniel Henrique Barboza
2024-05-07 15:35 ` Frank Chang
2024-05-07 15:37 ` [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU Frank Chang
2024-05-07 15:53 ` Gerd Hoffmann
2024-05-08 11:19 ` Daniel Henrique Barboza
2024-05-08 11:17 ` Daniel Henrique Barboza
2024-05-07 15:44 ` Peter Maydell
2024-05-08 12:41 ` Daniel Henrique Barboza [this message]
2024-05-10 10:47 ` Frank Chang
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