From: BALATON Zoltan <balaton@eik.bme.hu>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
Daniel Henrique Barboza <danielhb413@gmail.com>
Subject: [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate()
Date: Thu, 02 May 2024 01:43:24 +0200 (CEST) [thread overview]
Message-ID: <a35ae0f50258d4c4b8b6381bec9933f17105091a.1714606359.git.balaton@eik.bme.hu> (raw)
In-Reply-To: <cover.1714606359.git.balaton@eik.bme.hu>
Instead of putting a large block of code in an if, invert the
condition and return early to be able to deindent the code block.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/mmu_common.c | 319 ++++++++++++++++++++--------------------
1 file changed, 159 insertions(+), 160 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 28847c32f2..2487b4deff 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1265,187 +1265,186 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
*protp = ctx.prot;
*psizep = TARGET_PAGE_BITS;
return true;
+ } else if (!guest_visible) {
+ return false;
}
- if (guest_visible) {
- log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
- if (type == ACCESS_CODE) {
- switch (ret) {
- case -1:
- /* No matches in page tables or TLB */
- switch (env->mmu_model) {
- case POWERPC_MMU_SOFT_6xx:
- cs->exception_index = POWERPC_EXCP_IFTLB;
- env->error_code = 1 << 18;
- env->spr[SPR_IMISS] = eaddr;
- env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
- goto tlb_miss;
- case POWERPC_MMU_SOFT_4xx:
- cs->exception_index = POWERPC_EXCP_ITLB;
- env->error_code = 0;
- env->spr[SPR_40x_DEAR] = eaddr;
- env->spr[SPR_40x_ESR] = 0x00000000;
- break;
- case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
- /* fall through */
- case POWERPC_MMU_BOOKE:
- cs->exception_index = POWERPC_EXCP_ITLB;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
- break;
- case POWERPC_MMU_REAL:
- cpu_abort(cs, "PowerPC in real mode should never raise "
- "any MMU exceptions\n");
- default:
- cpu_abort(cs, "Unknown or invalid MMU model\n");
- }
+ log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
+ if (type == ACCESS_CODE) {
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_SOFT_6xx:
+ cs->exception_index = POWERPC_EXCP_IFTLB;
+ env->error_code = 1 << 18;
+ env->spr[SPR_IMISS] = eaddr;
+ env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
+ goto tlb_miss;
+ case POWERPC_MMU_SOFT_4xx:
+ cs->exception_index = POWERPC_EXCP_ITLB;
+ env->error_code = 0;
+ env->spr[SPR_40x_DEAR] = eaddr;
+ env->spr[SPR_40x_ESR] = 0x00000000;
break;
- case -2:
- /* Access rights violation */
- cs->exception_index = POWERPC_EXCP_ISI;
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->error_code = 0;
- } else {
- env->error_code = 0x08000000;
- }
+ case POWERPC_MMU_BOOKE206:
+ booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
+ /* fall through */
+ case POWERPC_MMU_BOOKE:
+ cs->exception_index = POWERPC_EXCP_ITLB;
+ env->error_code = 0;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD);
break;
- case -3:
- /* No execute protection violation */
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->spr[SPR_BOOKE_ESR] = 0x00000000;
- env->error_code = 0;
+ case POWERPC_MMU_REAL:
+ cpu_abort(cs, "PowerPC in real mode should never raise "
+ "any MMU exceptions\n");
+ default:
+ cpu_abort(cs, "Unknown or invalid MMU model\n");
+ }
+ break;
+ case -2:
+ /* Access rights violation */
+ cs->exception_index = POWERPC_EXCP_ISI;
+ if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+ (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+ env->error_code = 0;
+ } else {
+ env->error_code = 0x08000000;
+ }
+ break;
+ case -3:
+ /* No execute protection violation */
+ if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+ (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+ env->spr[SPR_BOOKE_ESR] = 0x00000000;
+ env->error_code = 0;
+ } else {
+ env->error_code = 0x10000000;
+ }
+ cs->exception_index = POWERPC_EXCP_ISI;
+ break;
+ case -4:
+ /* Direct store exception */
+ /* No code fetch is allowed in direct-store areas */
+ cs->exception_index = POWERPC_EXCP_ISI;
+ if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+ (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+ env->error_code = 0;
+ } else {
+ env->error_code = 0x10000000;
+ }
+ break;
+ }
+ } else {
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_SOFT_6xx:
+ if (access_type == MMU_DATA_STORE) {
+ cs->exception_index = POWERPC_EXCP_DSTLB;
+ env->error_code = 1 << 16;
} else {
- env->error_code = 0x10000000;
+ cs->exception_index = POWERPC_EXCP_DLTLB;
+ env->error_code = 0;
}
- cs->exception_index = POWERPC_EXCP_ISI;
+ env->spr[SPR_DMISS] = eaddr;
+ env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
+ tlb_miss:
+ env->error_code |= ctx.key << 19;
+ env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
+ get_pteg_offset32(cpu, ctx.hash[0]);
+ env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
+ get_pteg_offset32(cpu, ctx.hash[1]);
break;
- case -4:
- /* Direct store exception */
- /* No code fetch is allowed in direct-store areas */
- cs->exception_index = POWERPC_EXCP_ISI;
- if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->error_code = 0;
+ case POWERPC_MMU_SOFT_4xx:
+ cs->exception_index = POWERPC_EXCP_DTLB;
+ env->error_code = 0;
+ env->spr[SPR_40x_DEAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_40x_ESR] = 0x00800000;
} else {
- env->error_code = 0x10000000;
+ env->spr[SPR_40x_ESR] = 0x00000000;
}
break;
- }
- } else {
- switch (ret) {
- case -1:
- /* No matches in page tables or TLB */
- switch (env->mmu_model) {
- case POWERPC_MMU_SOFT_6xx:
- if (access_type == MMU_DATA_STORE) {
- cs->exception_index = POWERPC_EXCP_DSTLB;
- env->error_code = 1 << 16;
- } else {
- cs->exception_index = POWERPC_EXCP_DLTLB;
- env->error_code = 0;
- }
- env->spr[SPR_DMISS] = eaddr;
- env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
- tlb_miss:
- env->error_code |= ctx.key << 19;
- env->spr[SPR_HASH1] = ppc_hash32_hpt_base(cpu) +
- get_pteg_offset32(cpu, ctx.hash[0]);
- env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
- get_pteg_offset32(cpu, ctx.hash[1]);
- break;
- case POWERPC_MMU_SOFT_4xx:
- cs->exception_index = POWERPC_EXCP_DTLB;
- env->error_code = 0;
- env->spr[SPR_40x_DEAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_40x_ESR] = 0x00800000;
- } else {
- env->spr[SPR_40x_ESR] = 0x00000000;
- }
- break;
- case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
- /* fall through */
- case POWERPC_MMU_BOOKE:
- cs->exception_index = POWERPC_EXCP_DTLB;
- env->error_code = 0;
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
- break;
- case POWERPC_MMU_REAL:
- cpu_abort(cs, "PowerPC in real mode should never raise "
+ case POWERPC_MMU_BOOKE206:
+ booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+ /* fall through */
+ case POWERPC_MMU_BOOKE:
+ cs->exception_index = POWERPC_EXCP_DTLB;
+ env->error_code = 0;
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ break;
+ case POWERPC_MMU_REAL:
+ cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
- default:
- cpu_abort(cs, "Unknown or invalid MMU model\n");
+ default:
+ cpu_abort(cs, "Unknown or invalid MMU model\n");
+ }
+ break;
+ case -2:
+ /* Access rights violation */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
+ env->spr[SPR_40x_DEAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_40x_ESR] |= 0x00800000;
}
+ } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
+ (env->mmu_model == POWERPC_MMU_BOOKE206)) {
+ env->spr[SPR_BOOKE_DEAR] = eaddr;
+ env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ } else {
+ env->spr[SPR_DAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x0A000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x08000000;
+ }
+ }
+ break;
+ case -4:
+ /* Direct store exception */
+ switch (type) {
+ case ACCESS_FLOAT:
+ /* Floating point load/store */
+ cs->exception_index = POWERPC_EXCP_ALIGN;
+ env->error_code = POWERPC_EXCP_ALIGN_FP;
+ env->spr[SPR_DAR] = eaddr;
break;
- case -2:
- /* Access rights violation */
+ case ACCESS_RES:
+ /* lwarx, ldarx or stwcx. */
cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
- if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
- env->spr[SPR_40x_DEAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_40x_ESR] |= 0x00800000;
- }
- } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
- (env->mmu_model == POWERPC_MMU_BOOKE206)) {
- env->spr[SPR_BOOKE_DEAR] = eaddr;
- env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+ env->spr[SPR_DAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06000000;
} else {
- env->spr[SPR_DAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x0A000000;
- } else {
- env->spr[SPR_DSISR] = 0x08000000;
- }
+ env->spr[SPR_DSISR] = 0x04000000;
}
break;
- case -4:
- /* Direct store exception */
- switch (type) {
- case ACCESS_FLOAT:
- /* Floating point load/store */
- cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = POWERPC_EXCP_ALIGN_FP;
- env->spr[SPR_DAR] = eaddr;
- break;
- case ACCESS_RES:
- /* lwarx, ldarx or stwcx. */
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x06000000;
- } else {
- env->spr[SPR_DSISR] = 0x04000000;
- }
- break;
- case ACCESS_EXT:
- /* eciwx or ecowx */
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_DSISR] = 0x06100000;
- } else {
- env->spr[SPR_DSISR] = 0x04100000;
- }
- break;
- default:
- printf("DSI: invalid exception (%d)\n", ret);
- cs->exception_index = POWERPC_EXCP_PROGRAM;
- env->error_code =
- POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
- env->spr[SPR_DAR] = eaddr;
- break;
+ case ACCESS_EXT:
+ /* eciwx or ecowx */
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (access_type == MMU_DATA_STORE) {
+ env->spr[SPR_DSISR] = 0x06100000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04100000;
}
break;
+ default:
+ printf("DSI: invalid exception (%d)\n", ret);
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
+ env->spr[SPR_DAR] = eaddr;
+ break;
}
+ break;
}
}
return false;
--
2.30.9
next prev parent reply other threads:[~2024-05-01 23:50 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 01/28] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 02/28] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 03/28] target/ppc: Simplify syscall exception handlers BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 04/28] target/ppc: Remove unused helper BALATON Zoltan
2024-05-07 9:18 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 05/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage BALATON Zoltan
2024-05-07 9:19 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 06/28] " BALATON Zoltan
2024-05-07 9:20 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 07/28] target/ppc/mmu_common.c: Remove unneeded local variable BALATON Zoltan
2024-05-07 9:30 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 08/28] target/ppc/mmu_common.c: Simplify checking for real mode BALATON Zoltan
2024-05-07 9:34 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 09/28] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU BALATON Zoltan
2024-05-07 9:36 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 10/28] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() BALATON Zoltan
2024-05-07 9:42 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 11/28] target/ppc/mmu_common.c: Rename get_bat_6xx_tlb() BALATON Zoltan
2024-05-07 9:43 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 12/28] target/ppc/mmu_common.c: Split out BookE cases before checking real mode BALATON Zoltan
2024-05-07 9:50 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 13/28] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() BALATON Zoltan
2024-05-07 9:58 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 14/28] target/ppc/mmu_common.c: Inline and remove check_physical() BALATON Zoltan
2024-05-07 10:00 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 15/28] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address() BALATON Zoltan
2024-05-07 10:03 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 16/28] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address() BALATON Zoltan
2024-05-07 10:04 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 17/28] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls BALATON Zoltan
2024-05-07 10:05 ` Nicholas Piggin
2024-05-01 23:43 ` BALATON Zoltan [this message]
2024-05-07 10:06 ` [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 19/28] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() BALATON Zoltan
2024-05-07 10:11 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static BALATON Zoltan
2024-05-07 10:47 ` Nicholas Piggin
2024-05-07 15:31 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 21/28] target/ppc: Move mmu_ctx_t definition to mmu_common.c BALATON Zoltan
2024-05-07 10:49 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function BALATON Zoltan
2024-05-07 11:35 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() BALATON Zoltan
2024-05-07 11:51 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb() BALATON Zoltan
2024-05-07 12:05 ` Nicholas Piggin
2024-05-07 23:40 ` BALATON Zoltan
2024-05-08 12:54 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() BALATON Zoltan
2024-05-07 12:15 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together BALATON Zoltan
2024-05-07 12:17 ` Nicholas Piggin
2024-05-07 12:31 ` BALATON Zoltan
2024-05-08 12:30 ` Nicholas Piggin
2024-05-08 23:33 ` BALATON Zoltan
2024-05-09 5:57 ` Nicholas Piggin
2024-05-07 15:54 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env BALATON Zoltan
2024-05-07 12:30 ` Nicholas Piggin
2024-05-07 16:02 ` BALATON Zoltan
2024-05-08 12:37 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init BALATON Zoltan
2024-05-07 12:40 ` Nicholas Piggin
2024-05-07 12:45 ` [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups Nicholas Piggin
2024-05-07 12:51 ` BALATON Zoltan
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