From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH 3/5] tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffff
Date: Fri, 3 May 2024 17:04:47 +0200 [thread overview]
Message-ID: <3524e1a3-42b5-40dd-b7f7-5749d7adb030@linaro.org> (raw)
In-Reply-To: <20240424170908.759043-5-richard.henderson@linaro.org>
On 24/4/24 19:09, Richard Henderson wrote:
> This may be treated as a 32-bit EQ/NE comparison against 0,
> which is in turn treated as a LTU/GEU comparison against 1.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/i386/tcg-target.c.inc | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2024-05-03 15:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-24 17:09 [PATCH 0/5] tcg: Misc improvements Richard Henderson
2024-04-24 17:09 ` [PATCH] target/arm: Restrict translation disabled alignment check to VMSA Richard Henderson
2024-05-03 14:58 ` Philippe Mathieu-Daudé
2024-05-03 14:59 ` Richard Henderson
2024-04-24 17:09 ` [PATCH 1/5] tcg: Add write_aofs to GVecGen3i Richard Henderson
2024-05-03 15:01 ` Philippe Mathieu-Daudé
2024-04-24 17:09 ` [PATCH 2/5] tcg/i386: Simplify immediate 8-bit logical vector shifts Richard Henderson
2024-04-24 17:09 ` [PATCH 3/5] tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffff Richard Henderson
2024-05-03 15:04 ` Philippe Mathieu-Daudé [this message]
2024-04-24 17:09 ` [PATCH 4/5] tcg/optimize: Optimize setcond with zmask Richard Henderson
2024-04-24 17:09 ` [PATCH 5/5] accel/tcg: Introduce CF_BP_PAGE Richard Henderson
2024-05-03 15:02 ` Philippe Mathieu-Daudé
2024-05-02 19:34 ` [PATCH 0/5] tcg: Misc improvements Richard Henderson
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