From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>, qemu-devel@nongnu.org
Cc: "Clément Chigot" <chigot@adacore.com>, qemu-stable@nongnu.org
Subject: Re: [PATCH] target/arm: Restrict translation disabled alignment check to VMSA
Date: Fri, 3 May 2024 07:59:29 -0700 [thread overview]
Message-ID: <2ee4256a-e0cb-4469-988b-8c7bf7e6fa09@linaro.org> (raw)
In-Reply-To: <4906224c-b37e-4480-adc7-362ad2023b36@linaro.org>
On 5/3/24 07:58, Philippe Mathieu-Daudé wrote:
> On 24/4/24 19:09, Richard Henderson wrote:
>> For cpus using PMSA, when the MPU is disabled, the default memory
>> type is Normal, Non-cachable.
>>
>> Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
>> Reported-by: Clément Chigot <chigot@adacore.com>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>
>> Since v9 will likely be tagged tomorrow without this fixed,
>> Cc: qemu-stable@nongnu.org
>>
>> ---
>> target/arm/tcg/hflags.c | 12 ++++++++++--
>> 1 file changed, 10 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
>> index 5da1b0fc1d..66de30b828 100644
>> --- a/target/arm/tcg/hflags.c
>> +++ b/target/arm/tcg/hflags.c
>> @@ -38,8 +38,16 @@ static bool aprofile_require_alignment(CPUARMState *env, int el,
>> uint64_t sctlr)
>> }
>> /*
>> - * If translation is disabled, then the default memory type is
>> - * Device(-nGnRnE) instead of Normal, which requires that alignment
>> + * With PMSA, when the MPU is disabled, all memory types in the
>> + * default map is Normal.
>> + */
>> + if (arm_feature(env, ARM_FEATURE_PMSA)) {
>> + return false;
>> + }
>> +
>> + /*
>> + * With VMSA, if translation is disabled, then the default memory type
>> + * is Device(-nGnRnE) instead of Normal, which requires that alignment
>> * be enforced. Since this affects all ram, it is most efficient
>> * to handle this during translation.
>> */
>
> This one is in target-arm.next:
> https://lore.kernel.org/qemu-devel/CAFEAcA98UrBLsAXKzLSkUnC2G_RZd56veqUkSGSttoADfkEKGA@mail.gmail.com/
Yes, that was a stray patch that accidentally got re-posted with this series.
r~
next prev parent reply other threads:[~2024-05-03 14:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-24 17:09 [PATCH 0/5] tcg: Misc improvements Richard Henderson
2024-04-24 17:09 ` [PATCH] target/arm: Restrict translation disabled alignment check to VMSA Richard Henderson
2024-05-03 14:58 ` Philippe Mathieu-Daudé
2024-05-03 14:59 ` Richard Henderson [this message]
2024-04-24 17:09 ` [PATCH 1/5] tcg: Add write_aofs to GVecGen3i Richard Henderson
2024-05-03 15:01 ` Philippe Mathieu-Daudé
2024-04-24 17:09 ` [PATCH 2/5] tcg/i386: Simplify immediate 8-bit logical vector shifts Richard Henderson
2024-04-24 17:09 ` [PATCH 3/5] tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffff Richard Henderson
2024-05-03 15:04 ` Philippe Mathieu-Daudé
2024-04-24 17:09 ` [PATCH 4/5] tcg/optimize: Optimize setcond with zmask Richard Henderson
2024-04-24 17:09 ` [PATCH 5/5] accel/tcg: Introduce CF_BP_PAGE Richard Henderson
2024-05-03 15:02 ` Philippe Mathieu-Daudé
2024-05-02 19:34 ` [PATCH 0/5] tcg: Misc improvements Richard Henderson
-- strict thread matches above, loose matches on Subject: below --
2024-04-22 17:07 [PATCH] target/arm: Restrict translation disabled alignment check to VMSA Richard Henderson
2024-04-22 17:09 ` Richard Henderson
2024-04-22 21:02 ` Philippe Mathieu-Daudé
2024-04-23 7:16 ` Clément Chigot
2024-04-25 19:18 ` Peter Maydell
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