From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Alistair Francis" <alistair@alistair23.me>,
"Cleber Rosa" <crosa@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Wainer dos Santos Moschetta" <wainersm@redhat.com>,
"Beraldo Leal" <bleal@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v3 02/16] aspeed/sli: Add AST2700 support
Date: Tue, 16 Apr 2024 17:18:49 +0800 [thread overview]
Message-ID: <20240416091904.935283-3-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240416091904.935283-1-jamin_lin@aspeedtech.com>
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce dummy AST2700 SLI and SLIIO models.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_sli.c | 178 +++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 3 +-
hw/misc/trace-events | 7 ++
include/hw/misc/aspeed_sli.h | 31 ++++++
4 files changed, 218 insertions(+), 1 deletion(-)
create mode 100644 hw/misc/aspeed_sli.c
create mode 100644 include/hw/misc/aspeed_sli.h
diff --git a/hw/misc/aspeed_sli.c b/hw/misc/aspeed_sli.c
new file mode 100644
index 0000000000..e84fd6a4ca
--- /dev/null
+++ b/hw/misc/aspeed_sli.c
@@ -0,0 +1,178 @@
+/*
+ * ASPEED SLI Controller
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/aspeed_sli.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+#define SLI_REGION_SIZE 0x500
+#define TO_REG(addr) ((addr) >> 2)
+
+static uint64_t aspeed_sli_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ AspeedSLIState *s = ASPEED_SLI(opaque);
+ int reg = TO_REG(addr);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return 0;
+ }
+
+ trace_aspeed_sli_read(addr, size, s->regs[reg]);
+ return s->regs[reg];
+}
+
+static void aspeed_sli_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedSLIState *s = ASPEED_SLI(opaque);
+ int reg = TO_REG(addr);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return;
+ }
+
+ trace_aspeed_sli_write(addr, size, data);
+ s->regs[reg] = data;
+}
+
+static uint64_t aspeed_sliio_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ AspeedSLIState *s = ASPEED_SLI(opaque);
+ int reg = TO_REG(addr);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return 0;
+ }
+
+ trace_aspeed_sliio_read(addr, size, s->regs[reg]);
+ return s->regs[reg];
+}
+
+static void aspeed_sliio_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedSLIState *s = ASPEED_SLI(opaque);
+ int reg = TO_REG(addr);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return;
+ }
+
+ trace_aspeed_sliio_write(addr, size, data);
+ s->regs[reg] = data;
+}
+
+static const MemoryRegionOps aspeed_sli_ops = {
+ .read = aspeed_sli_read,
+ .write = aspeed_sli_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static const MemoryRegionOps aspeed_sliio_ops = {
+ .read = aspeed_sliio_read,
+ .write = aspeed_sliio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_sli_realize(DeviceState *dev, Error **errp)
+{
+ AspeedSLIState *s = ASPEED_SLI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sli_ops, s,
+ TYPE_ASPEED_SLI, SLI_REGION_SIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_sliio_realize(DeviceState *dev, Error **errp)
+{
+ AspeedSLIState *s = ASPEED_SLI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sliio_ops, s,
+ TYPE_ASPEED_SLI, SLI_REGION_SIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_sli_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Aspeed SLI Controller";
+ dc->realize = aspeed_sli_realize;
+}
+
+static const TypeInfo aspeed_sli_info = {
+ .name = TYPE_ASPEED_SLI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedSLIState),
+ .class_init = aspeed_sli_class_init,
+ .class_size = sizeof(AspeedSLIClass),
+ .abstract = true,
+};
+
+static void aspeed_2700_sli_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "AST2700 SLI Controller";
+}
+
+static void aspeed_2700_sliio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "AST2700 I/O SLI Controller";
+ dc->realize = aspeed_sliio_realize;
+}
+
+static const TypeInfo aspeed_2700_sli_info = {
+ .name = TYPE_ASPEED_2700_SLI,
+ .parent = TYPE_ASPEED_SLI,
+ .class_init = aspeed_2700_sli_class_init,
+};
+
+static const TypeInfo aspeed_2700_sliio_info = {
+ .name = TYPE_ASPEED_2700_SLIIO,
+ .parent = TYPE_ASPEED_SLI,
+ .class_init = aspeed_2700_sliio_class_init,
+};
+
+static void aspeed_sli_register_types(void)
+{
+ type_register_static(&aspeed_sli_info);
+ type_register_static(&aspeed_2700_sli_info);
+ type_register_static(&aspeed_2700_sliio_info);
+}
+
+type_init(aspeed_sli_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 86596a3888..2ca8717be2 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -136,7 +136,8 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_sbc.c',
'aspeed_sdmc.c',
'aspeed_xdma.c',
- 'aspeed_peci.c'))
+ 'aspeed_peci.c',
+ 'aspeed_sli.c'))
system_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
system_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c'))
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 5d241cb40a..e13b648221 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -351,3 +351,10 @@ djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRI
# iosb.c
iosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
iosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
+
+# aspeed_sli.c
+aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+
diff --git a/include/hw/misc/aspeed_sli.h b/include/hw/misc/aspeed_sli.h
new file mode 100644
index 0000000000..2329002b84
--- /dev/null
+++ b/include/hw/misc/aspeed_sli.h
@@ -0,0 +1,31 @@
+/*
+ * ASPEED SLI Controller
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ASPEED_SLI_H
+#define ASPEED_SLI_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_SLI "aspeed.sli"
+#define TYPE_ASPEED_2700_SLI TYPE_ASPEED_SLI "-ast2700"
+#define TYPE_ASPEED_2700_SLIIO TYPE_ASPEED_SLI "io" "-ast2700"
+OBJECT_DECLARE_TYPE(AspeedSLIState, AspeedSLIClass, ASPEED_SLI)
+
+#define ASPEED_SLI_NR_REGS (0x500 >> 2)
+
+struct AspeedSLIState {
+ SysBusDevice parent;
+ MemoryRegion iomem;
+
+ uint32_t regs[ASPEED_SLI_NR_REGS];
+};
+
+struct AspeedSLIClass {
+ SysBusDeviceClass parent_class;
+};
+
+#endif /* ASPEED_SLI_H */
--
2.25.1
next prev parent reply other threads:[~2024-04-16 9:23 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-16 9:18 [PATCH v3 00/16] Add AST2700 support Jamin Lin via
2024-04-16 9:18 ` [PATCH v3 01/16] aspeed/wdt: " Jamin Lin via
2024-04-16 9:18 ` Jamin Lin via [this message]
2024-04-16 15:29 ` [PATCH v3 02/16] aspeed/sli: " Cédric Le Goater
2024-04-16 9:18 ` [PATCH v3 03/16] aspeed/sdmc: remove redundant macros Jamin Lin via
2024-04-16 15:30 ` Cédric Le Goater
2024-04-16 9:18 ` [PATCH v3 04/16] aspeed/sdmc: fix coding style Jamin Lin via
2024-04-16 15:30 ` Cédric Le Goater
2024-04-16 9:18 ` [PATCH v3 05/16] aspeed/sdmc: Add AST2700 support Jamin Lin via
2024-04-16 15:34 ` Cédric Le Goater
2024-04-16 9:18 ` [PATCH v3 06/16] aspeed/smc: correct device description Jamin Lin via
2024-04-16 15:34 ` Cédric Le Goater
2024-04-16 9:18 ` [PATCH v3 07/16] aspeed/smc: fix dma moving incorrect data length issue Jamin Lin via
2024-04-19 13:41 ` Cédric Le Goater
2024-04-30 7:22 ` Cédric Le Goater
2024-04-30 8:51 ` Jamin Lin
2024-05-03 14:35 ` Cédric Le Goater
2024-05-15 4:05 ` Jamin Lin
2024-04-16 9:18 ` [PATCH v3 08/16] aspeed/smc: support 64 bits dma dram address Jamin Lin via
2024-04-18 16:09 ` Cédric Le Goater
2024-04-19 6:00 ` Jamin Lin
2024-04-30 7:26 ` Cédric Le Goater
2024-04-30 7:56 ` Jamin Lin
2024-05-03 14:20 ` Cédric Le Goater
2024-05-15 8:56 ` Jamin Lin
2024-05-07 14:19 ` Cédric Le Goater
2024-05-15 9:01 ` Jamin Lin
2024-05-17 7:57 ` Cédric Le Goater
2024-05-20 2:40 ` Jamin Lin
2024-05-27 6:46 ` Cédric Le Goater
2024-05-27 6:48 ` Jamin Lin
2024-04-16 9:18 ` [PATCH v3 09/16] aspeed/smc: Add AST2700 support Jamin Lin via
2024-04-18 16:14 ` Cédric Le Goater
2024-04-16 9:18 ` [PATCH v3 10/16] aspeed/scu: " Jamin Lin via
2024-04-16 9:18 ` [PATCH v3 11/16] aspeed/intc: " Jamin Lin via
2024-05-07 13:33 ` Cédric Le Goater
2024-05-21 6:40 ` Jamin Lin
2024-05-21 7:44 ` Jamin Lin
2024-04-16 9:18 ` [PATCH v3 12/16] aspeed/soc: " Jamin Lin via
2024-04-19 7:10 ` Cédric Le Goater
2024-04-19 7:58 ` Jamin Lin
2024-05-17 7:58 ` Cédric Le Goater
2024-05-17 9:13 ` Jamin Lin
2024-05-07 13:06 ` Cédric Le Goater
2024-04-16 9:19 ` [PATCH v3 13/16] aspeed: Add an AST2700 eval board Jamin Lin via
2024-04-16 9:19 ` [PATCH v3 14/16] aspeed/soc: fix incorrect dram size for AST2700 Jamin Lin via
2024-04-16 9:19 ` [PATCH v3 15/16] test/avocado/machine_aspeed.py: Add AST2700 test case Jamin Lin via
2024-04-16 16:44 ` Cédric Le Goater
2024-04-16 9:19 ` [PATCH v3 16/16] docs:aspeed: Add AST2700 Evaluation board Jamin Lin via
2024-04-16 15:54 ` Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240416091904.935283-3-jamin_lin@aspeedtech.com \
--to=qemu-devel@nongnu.org \
--cc=alistair@alistair23.me \
--cc=andrew@codeconstruct.com.au \
--cc=bleal@redhat.com \
--cc=clg@kaod.org \
--cc=crosa@redhat.com \
--cc=jamin_lin@aspeedtech.com \
--cc=joel@jms.id.au \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=troy_lee@aspeedtech.com \
--cc=wainersm@redhat.com \
--cc=yunlin.tang@aspeedtech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).