From: Sebastian Huber <sebastian.huber@embedded-brains.de>
To: qemu-devel@nongnu.org
Subject: [PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI
Date: Fri, 9 Jul 2021 11:49:48 +0200 [thread overview]
Message-ID: <20210709094948.60344-1-sebastian.huber@embedded-brains.de> (raw)
According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case
since GIC_NCPU == 8.
For SPI, make the interrupt pending on all CPUs and not just the processor
targets of the interrupt.
This behaviour is at least present on the i.MX7D which uses an Cortex-A7MPCore.
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
hw/intc/arm_gic.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index a994b1f024..8e377bac59 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1294,12 +1294,14 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
for (i = 0; i < 8; i++) {
if (value & (1 << i)) {
+ int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
+
if (s->security_extn && !attrs.secure &&
!GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i));
+ GIC_DIST_SET_PENDING(irq + i, cm);
}
}
} else if (offset < 0x300) {
@@ -1317,11 +1319,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- /* ??? This currently clears the pending bit for all CPUs, even
- for per-CPU interrupts. It's unclear whether this is the
- corect behavior. */
if (value & (1 << i)) {
- GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
+ int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
+
+ GIC_DIST_CLEAR_PENDING(irq + i, cm);
}
}
} else if (offset < 0x380) {
--
2.26.2
next reply other threads:[~2021-07-09 9:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 9:49 Sebastian Huber [this message]
2021-07-23 14:04 ` [PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI Sebastian Huber
2021-07-23 14:12 ` Philippe Mathieu-Daudé
2021-07-25 8:08 ` Luc Michel
2021-07-26 8:04 ` Sebastian Huber
2021-07-26 13:02 ` Peter Maydell
2024-05-07 12:56 ` [PATCH 1/2] hw/intc/arm_gic: Fix set pending of PPIs Sebastian Huber
2024-05-07 12:56 ` [PATCH 2/2] hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn Sebastian Huber
2024-05-07 13:00 ` [PATCH 1/2] hw/intc/arm_gic: Fix set pending of PPIs Sebastian Huber
2024-05-07 13:00 ` [PATCH 2/2] hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn Sebastian Huber
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210709094948.60344-1-sebastian.huber@embedded-brains.de \
--to=sebastian.huber@embedded-brains.de \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).