From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH 29/55] target/arm: Implement MVE VMLALDAV
Date: Mon, 7 Jun 2021 17:57:55 +0100 [thread overview]
Message-ID: <20210607165821.9892-30-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org>
Implement the MVE VMLALDAV insn, which multiplies pairs of integer
elements, accumulating them into a 64-bit result in a pair of
general-purpose registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 8 +++
target/arm/translate.h | 10 ++++
target/arm/mve.decode | 15 ++++++
target/arm/mve_helper.c | 32 ++++++++++++
target/arm/translate-mve.c | 100 +++++++++++++++++++++++++++++++++++++
5 files changed, 165 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 66d31633cef..1013f6912da 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -146,3 +146,11 @@ DEF_HELPER_FLAGS_4(mve_vmulltsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+DEF_HELPER_FLAGS_4(mve_vmlaldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+
+DEF_HELPER_FLAGS_4(mve_vmlaldavuh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+DEF_HELPER_FLAGS_4(mve_vmlaldavuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 2821b325e33..99c917c571a 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -136,6 +136,11 @@ static inline int negate(DisasContext *s, int x)
return -x;
}
+static inline int plus_1(DisasContext *s, int x)
+{
+ return x + 1;
+}
+
static inline int plus_2(DisasContext *s, int x)
{
return x + 2;
@@ -151,6 +156,11 @@ static inline int times_4(DisasContext *s, int x)
return x * 4;
}
+static inline int times_2_plus_1(DisasContext *s, int x)
+{
+ return x * 2 + 1;
+}
+
static inline int arm_dc_feature(DisasContext *dc, int feature)
{
return (dc->features & (1ULL << feature)) != 0;
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 5a480d61cd6..bde54d05bb9 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -130,3 +130,18 @@ VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op
VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=0
VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size=1
VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2
+
+# multiply-add long dual accumulate
+# rdahi: bits [3:1] from insn, bit 0 is 1
+# rdalo: bits [3:1] from insn, bit 0 is 0
+%rdahi 20:3 !function=times_2_plus_1
+%rdalo 13:3 !function=times_2
+# size bit is 0 for 16 bit, 1 for 32 bit
+%size_16 16:1 !function=plus_1
+
+&vmlaldav rdahi rdalo size qn qm x a
+
+@vmlaldav .... .... . ... ... . ... . .... .... qm:3 . \
+ qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 &vmlaldav
+VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav
+VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 2d0c6998caa..3c7a0bac3c7 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -475,3 +475,35 @@ DO_2OP_S(vhadds, do_vhadd_s)
DO_2OP_U(vhaddu, do_vhadd_u)
DO_2OP_S(vhsubs, do_vhsub_s)
DO_2OP_U(vhsubu, do_vhsub_u)
+
+
+/*
+ * Multiply add long dual accumulate ops.
+ */
+#define DO_LDAV(OP, ESIZE, TYPE, H, XCHG, EVENACC, ODDACC) \
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
+ void *vm, uint64_t a) \
+ { \
+ uint16_t mask = mve_element_mask(env); \
+ unsigned e; \
+ TYPE *n = vn, *m = vm; \
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
+ if (mask & 1) { \
+ if (e & 1) { \
+ a ODDACC (int64_t)n[H(e - 1 * XCHG)] * m[H(e)]; \
+ } else { \
+ a EVENACC (int64_t)n[H(e + 1 * XCHG)] * m[H(e)]; \
+ } \
+ } \
+ } \
+ mve_advance_vpt(env); \
+ return a; \
+ }
+
+DO_LDAV(vmlaldavsh, 2, int16_t, H2, false, +=, +=)
+DO_LDAV(vmlaldavxsh, 2, int16_t, H2, true, +=, +=)
+DO_LDAV(vmlaldavsw, 4, int32_t, H4, false, +=, +=)
+DO_LDAV(vmlaldavxsw, 4, int32_t, H4, true, +=, +=)
+
+DO_LDAV(vmlaldavuh, 2, uint16_t, H2, false, +=, +=)
+DO_LDAV(vmlaldavuw, 4, uint32_t, H4, false, +=, +=)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index ccff7fc0ecf..03d9496f17d 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -31,6 +31,7 @@
typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
+typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
static inline long mve_qreg_offset(unsigned reg)
@@ -79,6 +80,22 @@ static void mve_update_eci(DisasContext *s)
}
}
+static bool mve_skip_first_beat(DisasContext *s)
+{
+ /* Return true if PSR.ECI says we must skip the first beat of this insn */
+ switch (s->eci) {
+ case ECI_NONE:
+ return false;
+ case ECI_A0:
+ case ECI_A0A1:
+ case ECI_A0A1A2:
+ case ECI_A0A1A2B0:
+ return true;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
{
TCGv_i32 addr;
@@ -397,3 +414,86 @@ DO_2OP(VMULL_BS, vmullbs)
DO_2OP(VMULL_BU, vmullbu)
DO_2OP(VMULL_TS, vmullts)
DO_2OP(VMULL_TU, vmulltu)
+
+static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
+ MVEGenDualAccOpFn *fn)
+{
+ TCGv_ptr qn, qm;
+ TCGv_i64 rda;
+ TCGv_i32 rdalo, rdahi;
+
+ if (!fn || !dc_isar_feature(aa32_mve, s)) {
+ return false;
+ }
+ /*
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
+ */
+ if (a->rdahi == 13 || a->rdahi == 15) {
+ return false;
+ }
+ if (a->qn > 7 || a->qm > 7) {
+ return false;
+ }
+ if (!mve_eci_check(s)) {
+ return true;
+ }
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ qn = mve_qreg_ptr(a->qn);
+ qm = mve_qreg_ptr(a->qm);
+
+ /*
+ * This insn is subject to beat-wise execution. Partial execution
+ * of an A=0 (no-accumulate) insn which does not execute the first
+ * beat must start with the current rda value, not 0.
+ */
+ if (a->a || mve_skip_first_beat(s)) {
+ rda = tcg_temp_new_i64();
+ rdalo = load_reg(s, a->rdalo);
+ rdahi = load_reg(s, a->rdahi);
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+ tcg_temp_free_i32(rdalo);
+ tcg_temp_free_i32(rdahi);
+ } else {
+ rda = tcg_const_i64(0);
+ }
+
+ fn(rda, cpu_env, qn, qm, rda);
+ tcg_temp_free_ptr(qn);
+ tcg_temp_free_ptr(qm);
+
+ rdalo = tcg_temp_new_i32();
+ rdahi = tcg_temp_new_i32();
+ tcg_gen_extrl_i64_i32(rdalo, rda);
+ tcg_gen_extrh_i64_i32(rdahi, rda);
+ store_reg(s, a->rdalo, rdalo);
+ store_reg(s, a->rdahi, rdahi);
+ tcg_temp_free_i64(rda);
+ mve_update_eci(s);
+ return true;
+}
+
+static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a)
+{
+ MVEGenDualAccOpFn *fns[4][2] = {
+ { NULL, NULL },
+ { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh },
+ { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw },
+ { NULL, NULL },
+ };
+ return do_long_dual_acc(s, a, fns[a->size][a->x]);
+}
+
+static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a)
+{
+ MVEGenDualAccOpFn *fns[4][2] = {
+ { NULL, NULL },
+ { gen_helper_mve_vmlaldavuh, NULL },
+ { gen_helper_mve_vmlaldavuw, NULL },
+ { NULL, NULL },
+ };
+ return do_long_dual_acc(s, a, fns[a->size][a->x]);
+}
--
2.20.1
next prev parent reply other threads:[~2021-06-07 17:19 UTC|newest]
Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 16:57 [PATCH 00/55] target/arm: First slice of MVE implementation Peter Maydell
2021-06-07 16:57 ` [PATCH 01/55] tcg: Introduce tcg_remove_ops_after Peter Maydell
2021-06-07 16:57 ` [PATCH 02/55] target/arm: Enable FPSCR.QC bit for MVE Peter Maydell
2021-06-07 19:02 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 03/55] target/arm: Handle VPR semantics in existing code Peter Maydell
2021-06-07 21:19 ` Richard Henderson
2021-06-10 9:28 ` Peter Maydell
2021-06-07 16:57 ` [PATCH 04/55] target/arm: Add handling for PSR.ECI/ICI Peter Maydell
2021-06-07 23:33 ` Richard Henderson
2021-06-10 10:17 ` Peter Maydell
2021-06-10 13:39 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 05/55] target/arm: Let vfp_access_check() handle late NOCP checks Peter Maydell
2021-06-07 23:50 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 06/55] target/arm: Implement MVE LCTP Peter Maydell
2021-06-08 0:05 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 07/55] target/arm: Implement MVE WLSTP insn Peter Maydell
2021-06-08 1:42 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 08/55] target/arm: Implement MVE DLSTP Peter Maydell
2021-06-08 2:56 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 09/55] target/arm: Implement MVE LETP insn Peter Maydell
2021-06-08 3:40 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 10/55] target/arm: Add framework for MVE decode Peter Maydell
2021-06-08 3:59 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 11/55] target/arm: Implement MVE VLDR/VSTR (non-widening forms) Peter Maydell
2021-06-08 21:33 ` Richard Henderson
2021-06-08 21:43 ` Richard Henderson
2021-06-09 10:01 ` Peter Maydell
2021-06-09 17:09 ` Richard Henderson
2021-06-10 14:01 ` Peter Maydell
2021-06-07 16:57 ` [PATCH 12/55] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns Peter Maydell
2021-06-08 21:46 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 13/55] target/arm: Implement MVE VCLZ Peter Maydell
2021-06-08 22:10 ` Richard Henderson
2021-06-10 12:40 ` Peter Maydell
2021-06-10 14:03 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 14/55] target/arm: Implement MVE VCLS Peter Maydell
2021-06-08 22:12 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 15/55] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations Peter Maydell
2021-06-08 6:53 ` Philippe Mathieu-Daudé
2021-06-08 22:14 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 16/55] target/arm: Implement MVE VREV16, VREV32, VREV64 Peter Maydell
2021-06-08 22:23 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 17/55] target/arm: Implement MVE VMVN (register) Peter Maydell
2021-06-08 22:27 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 18/55] target/arm: Implement MVE VABS Peter Maydell
2021-06-08 22:34 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 19/55] target/arm: Implement MVE VNEG Peter Maydell
2021-06-08 22:40 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 20/55] target/arm: Implement MVE VDUP Peter Maydell
2021-06-08 23:17 ` Richard Henderson
2021-06-09 10:06 ` Peter Maydell
2021-06-09 17:16 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR Peter Maydell
2021-06-08 23:23 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 22/55] target/arm: Implement MVE VADD, VSUB, VMUL Peter Maydell
2021-06-08 23:25 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 23/55] target/arm: Implement MVE VMULH Peter Maydell
2021-06-08 23:29 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 24/55] target/arm: Implement MVE VRMULH Peter Maydell
2021-06-08 23:33 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 25/55] target/arm: Implement MVE VMAX, VMIN Peter Maydell
2021-06-08 23:35 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 26/55] target/arm: Implement MVE VABD Peter Maydell
2021-06-08 23:39 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 27/55] target/arm: Implement MVE VHADD, VHSUB Peter Maydell
2021-06-08 23:43 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 28/55] target/arm: Implement MVE VMULL Peter Maydell
2021-06-08 23:52 ` Richard Henderson
2021-06-07 16:57 ` Peter Maydell [this message]
2021-06-09 0:46 ` [PATCH 29/55] target/arm: Implement MVE VMLALDAV Richard Henderson
2021-06-09 0:46 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 30/55] target/arm: Implement MVE VMLSLDAV Peter Maydell
2021-06-09 0:47 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 31/55] include/qemu/int128.h: Add function to create Int128 from int64_t Peter Maydell
2021-06-08 6:45 ` Philippe Mathieu-Daudé
2021-06-09 0:51 ` Richard Henderson
2021-06-07 16:57 ` [PATCH 32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH Peter Maydell
2021-06-09 1:05 ` Richard Henderson
2021-06-14 10:19 ` Peter Maydell
2021-06-07 16:57 ` [PATCH 33/55] target/arm: Implement MVE VADD (scalar) Peter Maydell
2021-06-09 17:58 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 34/55] target/arm: Implement MVE VSUB, VMUL (scalar) Peter Maydell
2021-06-09 18:00 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 35/55] target/arm: Implement MVE VHADD, VHSUB (scalar) Peter Maydell
2021-06-09 18:02 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 36/55] target/arm: Implement MVE VBRSR Peter Maydell
2021-06-09 18:08 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 37/55] target/arm: Implement MVE VPST Peter Maydell
2021-06-09 18:23 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 38/55] target/arm: Implement MVE VQADD and VQSUB Peter Maydell
2021-06-09 18:46 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 39/55] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) Peter Maydell
2021-06-09 18:58 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 40/55] target/arm: Implement MVE VQDMULL scalar Peter Maydell
2021-06-09 19:11 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 41/55] target/arm: Implement MVE VQDMULH, VQRDMULH (vector) Peter Maydell
2021-06-09 19:13 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 42/55] target/arm: Implement MVE VQADD, VQSUB (vector) Peter Maydell
2021-06-09 19:15 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 43/55] target/arm: Implement MVE VQSHL (vector) Peter Maydell
2021-06-09 19:26 ` Richard Henderson
2021-06-14 11:04 ` Peter Maydell
2021-06-07 16:58 ` [PATCH 44/55] target/arm: Implement MVE VQRSHL Peter Maydell
2021-06-09 19:29 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 45/55] target/arm: Implement MVE VSHL insn Peter Maydell
2021-06-09 19:40 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 46/55] target/arm: Implement MVE VRSHL Peter Maydell
2021-06-09 19:43 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 47/55] target/arm: Implement MVE VQDMLADH and VQRDMLADH Peter Maydell
2021-06-09 20:05 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 48/55] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH Peter Maydell
2021-06-09 20:08 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 49/55] target/arm: Implement MVE VQDMULL (vector) Peter Maydell
2021-06-09 20:20 ` Richard Henderson
2021-06-10 19:08 ` Peter Maydell
2021-06-10 19:34 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 50/55] target/arm: Implement MVE VRHADD Peter Maydell
2021-06-09 20:24 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 51/55] target/arm: Implement MVE VADC, VSBC Peter Maydell
2021-06-09 21:06 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 52/55] target/arm: Implement MVE VCADD Peter Maydell
2021-06-09 21:16 ` Richard Henderson
2021-06-10 19:16 ` Peter Maydell
2021-06-07 16:58 ` [PATCH 53/55] target/arm: Implement MVE VHCADD Peter Maydell
2021-06-10 3:50 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 54/55] target/arm: Implement MVE VADDV Peter Maydell
2021-06-10 14:06 ` Richard Henderson
2021-06-07 16:58 ` [PATCH 55/55] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE Peter Maydell
2021-06-10 14:14 ` Richard Henderson
2021-06-09 14:33 ` [PATCH 00/55] target/arm: First slice of MVE implementation no-reply
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