From: Tianyang Zhang <zhangtianyang@loongson.cn>
To: Randy Dunlap <rdunlap@infradead.org>,
chenhuacai@kernel.org, kernel@xen0n.name, corbet@lwn.net,
alexs@kernel.org, siyanteng@loongson.cn
Cc: loongarch@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] docs: Add advanced extended IRQ model description
Date: Mon, 13 May 2024 14:40:23 +0800 [thread overview]
Message-ID: <a72f2d5b-ed6d-1b47-ac99-5c99f9cf257b@loongson.cn> (raw)
In-Reply-To: <c1f1b699-71ad-409a-a843-afe42640626a@infradead.org>
在 2024/5/9 上午6:29, Randy Dunlap 写道:
> Hi--
>
> On 5/7/24 5:22 AM, Tianyang Zhang wrote:
>> From 3C6000, Loongarch began to support advanced extended
>> interrupt mode, in which each CPU has an independent interrupt
>> vector number.This will enhance the architecture's ability
>> to support modern devices
>>
>> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
>> ---
>> .../arch/loongarch/irq-chip-model.rst | 33 +++++++++++++++++
>> .../zh_CN/arch/loongarch/irq-chip-model.rst | 37 +++++++++++++++++--
>> 2 files changed, 67 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst
>> index 7988f4192363..79228741d1b9 100644
>> --- a/Documentation/arch/loongarch/irq-chip-model.rst
>> +++ b/Documentation/arch/loongarch/irq-chip-model.rst
>> @@ -85,6 +85,39 @@ to CPUINTC directly::
>> | Devices |
>> +---------+
>>
>> +Advanced Extended IRQ model
>> +=======================
> The === underline line needs to be at least as long as the line above it.
I will repair this problem
>> +
>> +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
>> +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, MSI interrupts go to AVEC,
>> +and then go to CPUINTC, Other devices interrupts go to PCH-PIC/PCH-LPC and gathered
> CPUINTC.
Thank you for the reminder
>> +by EIOINTC, and then go to CPUINTC directly::
>> +
>> + +-----+ +--------------------------+ +-------+
>> + | IPI | --> | CPUINTC | <-- | Timer |
>> + +-----+ +--------------------------+ +-------+
>> + ^ ^ ^
>> + | | |
>> + +--------+ +---------+ +---------+ +-------+
>> + | AVEC | | EIOINTC | | LIOINTC | <-- | UARTs |
>> + +--------+ +---------+ +---------+ +-------+
>> + ^ ^
>> + | |
>> + +---------+ +---------+
>> + | MSI | | PCH-PIC |
>> + +---------+ +---------+
>> + ^ ^ ^
>> + | | |
>> + +---------+ +---------+ +---------+
>> + | Devices | | PCH-LPC | | Devices |
>> + +---------+ +---------+ +---------+
>> + ^
>> + |
>> + +---------+
>> + | Devices |
>> + +---------+
>> +
>> +
>> ACPI-related definitions
>> ========================
>>
> thanks.
next prev parent reply other threads:[~2024-05-13 6:40 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 12:22 [PATCH 1/2] docs: Add advanced extended IRQ model description Tianyang Zhang
2024-05-08 22:29 ` Randy Dunlap
2024-05-13 6:40 ` Tianyang Zhang [this message]
2024-05-09 2:24 ` Dongliang Mu
2024-05-13 6:38 ` Tianyang Zhang
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