From: Tianyang Zhang <zhangtianyang@loongson.cn>
To: Dongliang Mu <mudongliangabcd@gmail.com>
Cc: chenhuacai@kernel.org, kernel@xen0n.name, corbet@lwn.net,
alexs@kernel.org, siyanteng@loongson.cn,
loongarch@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] docs: Add advanced extended IRQ model description
Date: Mon, 13 May 2024 14:38:36 +0800 [thread overview]
Message-ID: <5648b40a-51fa-612d-d102-e2948866174f@loongson.cn> (raw)
In-Reply-To: <CAD-N9QV82w1_7ksGAWJDNVcRDyKHLgiEbx13b3sr4cTazobW5g@mail.gmail.com>
在 2024/5/9 上午10:24, Dongliang Mu 写道:
> On Tue, May 7, 2024 at 8:24 PM Tianyang Zhang <zhangtianyang@loongson.cn> wrote:
>> From 3C6000, Loongarch began to support advanced extended
>> interrupt mode, in which each CPU has an independent interrupt
>> vector number.This will enhance the architecture's ability
>> to support modern devices
>>
>> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
>> ---
>> .../arch/loongarch/irq-chip-model.rst | 33 +++++++++++++++++
>> .../zh_CN/arch/loongarch/irq-chip-model.rst | 37 +++++++++++++++++--
>> 2 files changed, 67 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst
>> index 7988f4192363..79228741d1b9 100644
>> --- a/Documentation/arch/loongarch/irq-chip-model.rst
>> +++ b/Documentation/arch/loongarch/irq-chip-model.rst
>> @@ -85,6 +85,39 @@ to CPUINTC directly::
>> | Devices |
>> +---------+
>>
>> +Advanced Extended IRQ model
>> +=======================
>> +
>> +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
>> +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, MSI interrupts go to AVEC,
>> +and then go to CPUINTC, Other devices interrupts go to PCH-PIC/PCH-LPC and gathered
>> +by EIOINTC, and then go to CPUINTC directly::
>> +
>> + +-----+ +--------------------------+ +-------+
>> + | IPI | --> | CPUINTC | <-- | Timer |
>> + +-----+ +--------------------------+ +-------+
>> + ^ ^ ^
>> + | | |
>> + +--------+ +---------+ +---------+ +-------+
>> + | AVEC | | EIOINTC | | LIOINTC | <-- | UARTs |
>> + +--------+ +---------+ +---------+ +-------+
>> + ^ ^
>> + | |
>> + +---------+ +---------+
>> + | MSI | | PCH-PIC |
>> + +---------+ +---------+
>> + ^ ^ ^
>> + | | |
>> + +---------+ +---------+ +---------+
>> + | Devices | | PCH-LPC | | Devices |
>> + +---------+ +---------+ +---------+
>> + ^
>> + |
>> + +---------+
>> + | Devices |
>> + +---------+
>> +
>> +
>> ACPI-related definitions
>> ========================
>>
>> diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst
>> index f1e9ab18206c..7ccde82dd666 100644
>> --- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst
>> +++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst
>> @@ -9,9 +9,8 @@
>> LoongArch的IRQ芯片模型（层级关系）
>> ==================================
>>
>> -目前，基于LoongArch的处理器（如龙芯3A5000）只能与LS7A芯片组配合工作。LoongArch计算机
>> -中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
>> -Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
>> +LoongArch计算机中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、
>> +LIOINTC（Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
>> HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
>> 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
>>
>> @@ -87,6 +86,38 @@ PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
>> | Devices |
>> +---------+
>>
>> +高级扩展IRQ模型
>> +=======================
>> +
>> +在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
>> +CPU串口（UARTs）中断发送到LIOINTC，MSI中断发送到AVEC,而后通过AVEC送达CPUINTC，而
> AVEC is followed by an English comma (Translation: AVEC 后面一个英文逗号)
> Dongliang Mu
Ok, I will follow the advice
>> +其他所有设备的中断则分别发送到所连接的PCH-PIC/PCH-LPC，然后由EIOINTC统一收集，再直
>> +接到达CPUINTC::
>> +
>> + +-----+ +--------------------------+ +-------+
>> + | IPI | --> | CPUINTC | <-- | Timer |
>> + +-----+ +--------------------------+ +-------+
>> + ^ ^ ^
>> + | | |
>> + +--------+ +---------+ +---------+ +-------+
>> + | AVEC | | EIOINTC | | LIOINTC | <-- | UARTs |
>> + +--------+ +---------+ +---------+ +-------+
>> + ^ ^
>> + | |
>> + +---------+ +-------------+
>> + | MSI | | PCH-PIC |
>> + +---------+ +-------------+
>> + ^ ^ ^
>> + | | |
>> + +---------+ +---------+ +---------+
>> + | Devices | | PCH-LPC | | Devices |
>> + +---------+ +---------+ +---------+
>> + ^
>> + |
>> + +---------+
>> + | Devices |
>> + +---------+
>> +
>> ACPI相关的定义
>> ==============
>>
>> --
>> 2.20.1
>>
>>
prev parent reply other threads:[~2024-05-13 6:38 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 12:22 [PATCH 1/2] docs: Add advanced extended IRQ model description Tianyang Zhang
2024-05-08 22:29 ` Randy Dunlap
2024-05-13 6:40 ` Tianyang Zhang
2024-05-09 2:24 ` Dongliang Mu
2024-05-13 6:38 ` Tianyang Zhang [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5648b40a-51fa-612d-d102-e2948866174f@loongson.cn \
--to=zhangtianyang@loongson.cn \
--cc=alexs@kernel.org \
--cc=chenhuacai@kernel.org \
--cc=corbet@lwn.net \
--cc=kernel@xen0n.name \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=loongarch@lists.linux.dev \
--cc=mudongliangabcd@gmail.com \
--cc=siyanteng@loongson.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).