From: Liankun Yang <liankun.yang@mediatek.com>
To: <chunkuang.hu@kernel.org>, <p.zabel@pengutronix.de>,
<chunfeng.yun@mediatek.com>, <vkoul@kernel.org>,
<kishon@kernel.org>, <matthias.bgg@gmail.com>,
<angelogioacchino.delregno@collabora.com>,
<jitao.shi@mediatek.com>, <mac.shen@mediatek.com>,
<liankun.yang@mediatek.com>
Cc: <dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v1 1/1] drm/mediatek/dp: The register is written with the parsed DTS SSC value.
Date: Wed, 3 Apr 2024 12:05:09 +0800 [thread overview]
Message-ID: <20240403040517.3279-1-liankun.yang@mediatek.com> (raw)
[Description]
Severe screen flickering has been observed on the external display
when the DP projection function is used with the market expansion dock.
[Root cause]
It has been discovered through analysis that severe screen flickering
will occur when using the current default settings of
SC (Spread Spectrum Clocking) after it is opened.
[Solution]
Reducing SSC capability on the test platform can
resolve the screen flickering issue.
By configuring SSC parameters in DTS, locating the DP SSC node
in phy-mtk-dp, parsing the current value of SSC, and writing this value
into PHY to configure SSC can solve the screen flickering problem.
[Test]
The SSC configuration values are read from DTS, parsed in the driver,
and then written to the hardware. The test results indicate that
there is no screen flickering.
Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-dp.c | 61 +++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index d7024a144335..13e5d3c33784 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c
@@ -25,6 +25,10 @@
#define BIT_RATE_HBR2 2
#define BIT_RATE_HBR3 3
+#define MTK_DP_PHY_DIG_GLB_DA_REG_14 (PHY_OFFSET + 0xD8)
+#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT GENMASK(15, 0)
+#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT GENMASK(31, 16)
+
#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38)
#define DP_GLB_SW_RST_PHYD BIT(0)
@@ -78,10 +82,57 @@
#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
+#define SSC_SETTING "dp-ssc-setting"
+#define RG_XTP_GLB_TXPLL_SSC_DELTA_RBR "ssc-delta-rbr"
+#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR "ssc-delta-hbr"
+
struct mtk_dp_phy {
struct regmap *regs;
+ struct device *dev;
};
+static int mtk_dp_set_ssc_config(struct phy *phy, struct mtk_dp_phy *dp_phy,
+ struct device_node *ssc_node, const char *mode_name, u32 ssc_reg_offset)
+{
+ int ret;
+ u32 read_value = 0;
+
+ ret = of_property_read_u32(ssc_node, mode_name, &read_value);
+ if (ret) {
+ dev_err(&phy->dev, "Read fail,DPTX is not %s\n", mode_name);
+ return -EINVAL;
+ }
+
+ if (!read_value) {
+ dev_err(&phy->dev, "Read value is NULL\n");
+ return -ENOMEM;
+ }
+
+ if (!strcmp(mode_name, RG_XTP_GLB_TXPLL_SSC_DELTA_RBR)) {
+ regmap_update_bits(dp_phy->regs, ssc_reg_offset,
+ XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT, read_value);
+ } else if (!strcmp(mode_name, RG_XTP_GLB_TXPLL_SSC_DELTA_HBR)) {
+ read_value = read_value << 16 | 0x0000;
+ regmap_update_bits(dp_phy->regs, ssc_reg_offset,
+ XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT, read_value);
+ }
+
+ return 0;
+}
+
+static struct device_node *mtk_dp_get_ssc_node(struct phy *phy, struct mtk_dp_phy *dp_phy)
+{
+ struct device_node *mode_node = NULL;
+
+ mode_node = of_find_node_by_name(dp_phy->dev->of_node, SSC_SETTING);
+ if (!mode_node) {
+ dev_err(&phy->dev, "SSC node is NULL\n");
+ return NULL;
+ }
+
+ return mode_node;
+}
+
static int mtk_dp_phy_init(struct phy *phy)
{
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
@@ -109,6 +160,7 @@ static int mtk_dp_phy_init(struct phy *phy)
static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
{
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
+ struct device_node *ssc_node = NULL;
u32 val;
if (opts->dp.set_rate) {
@@ -137,6 +189,14 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
+ ssc_node = mtk_dp_get_ssc_node(phy, dp_phy);
+ if (ssc_node) {
+ mtk_dp_set_ssc_config(phy, dp_phy, ssc_node, RG_XTP_GLB_TXPLL_SSC_DELTA_RBR,
+ MTK_DP_PHY_DIG_GLB_DA_REG_14);
+ mtk_dp_set_ssc_config(phy, dp_phy, ssc_node, RG_XTP_GLB_TXPLL_SSC_DELTA_HBR,
+ MTK_DP_PHY_DIG_GLB_DA_REG_14);
+ }
+
return 0;
}
@@ -186,6 +246,7 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
if (!dev->of_node)
phy_create_lookup(phy, "dp", dev_name(dev));
+ dp_phy->dev = dev;
return 0;
}
--
2.43.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next reply other threads:[~2024-04-03 4:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 4:05 Liankun Yang [this message]
2024-04-03 6:41 ` [PATCH v1 1/1] drm/mediatek/dp: The register is written with the parsed DTS SSC value Krzysztof Kozlowski
2024-04-03 14:56 ` Krzysztof Kozlowski
2024-04-11 6:30 ` LIANKUN YANG (杨连坤)
2024-04-11 6:37 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240403040517.3279-1-liankun.yang@mediatek.com \
--to=liankun.yang@mediatek.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=chunfeng.yun@mediatek.com \
--cc=chunkuang.hu@kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=jitao.shi@mediatek.com \
--cc=kishon@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-phy@lists.infradead.org \
--cc=mac.shen@mediatek.com \
--cc=matthias.bgg@gmail.com \
--cc=p.zabel@pengutronix.de \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).