From: Dan Carpenter <dan.carpenter@linaro.org>
To: shubhrajyoti.datta@amd.com
Cc: linux-edac@vger.kernel.org
Subject: [bug report] EDAC/versal: Add a Xilinx Versal memory controller driver
Date: Fri, 20 Oct 2023 16:45:57 +0300 [thread overview]
Message-ID: <a4db6f93-8e5f-4d55-a7b8-b5a987d48a58@moroto.mountain> (raw)
Hello Shubhrajyoti Datta,
The patch 0fd934580ea3: "EDAC/versal: Add a Xilinx Versal memory
controller driver" from Oct 5, 2023 (linux-next), leads to the
following Smatch static checker warning:
drivers/edac/versal_edac.c:967 mc_probe()
warn: unsigned 'edac_mc_id' is never less than zero.
drivers/edac/versal_edac.c
944 static int mc_probe(struct platform_device *pdev)
945 {
946 void __iomem *ddrmc_baseaddr, *ddrmc_noc_baseaddr;
947 struct edac_mc_layer layers[2];
948 struct mem_ctl_info *mci;
949 u8 num_chans, num_csrows;
950 struct edac_priv *priv;
951 u32 edac_mc_id, regval;
^^^^^^^^^^^^^^
952 int rc;
953
954 ddrmc_baseaddr = devm_platform_ioremap_resource_byname(pdev, "base");
955 if (IS_ERR(ddrmc_baseaddr))
956 return PTR_ERR(ddrmc_baseaddr);
957
958 ddrmc_noc_baseaddr = devm_platform_ioremap_resource_byname(pdev, "noc");
959 if (IS_ERR(ddrmc_noc_baseaddr))
960 return PTR_ERR(ddrmc_noc_baseaddr);
961
962 if (!get_ecc_state(ddrmc_baseaddr))
963 return -ENXIO;
964
965 /* Allocate ID number for our EMIF controller */
966 edac_mc_id = emif_get_id(pdev->dev.of_node);
--> 967 if (edac_mc_id < 0)
emif_get_id() doesn't return error pointers and edac_mc_id is unsigned
so this won't work.
968 return -EINVAL;
969
970 regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);
971 num_chans = FIELD_PREP(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval);
972 num_chans++;
973
974 num_csrows = FIELD_PREP(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval);
975 num_csrows *= 2;
976 if (!num_csrows)
977 num_csrows = 1;
regards,
dan carpenter
next reply other threads:[~2023-10-20 13:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-20 13:45 Dan Carpenter [this message]
2023-10-20 15:41 ` [bug report] EDAC/versal: Add a Xilinx Versal memory controller driver Borislav Petkov
2023-10-24 5:43 ` Datta, Shubhrajyoti
2023-10-24 9:25 ` Borislav Petkov
2023-10-24 9:29 ` Datta, Shubhrajyoti
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