From: Anand Moon <linux.amoon@gmail.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Anand Moon <linux.amoon@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCHv1 1/5] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC
Date: Mon, 5 Feb 2024 22:49:19 +0530 [thread overview]
Message-ID: <20240205171930.968-2-linux.amoon@gmail.com> (raw)
In-Reply-To: <20240205171930.968-1-linux.amoon@gmail.com>
As per S905 and S905X datasheet add missing cache information to
the Amlogic GXBB and GXL SoC.
- Each Cortex-A53 core has 32KB of L1 instruction cache available and
32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.
To improve system performance.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
Datasheet
[0] https://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 2673f0dbafe7..e141ade5e49b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -95,6 +95,12 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@@ -105,6 +111,12 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@@ -115,6 +127,12 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@@ -125,6 +143,12 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@@ -134,6 +158,9 @@ l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x7d000>; /* L2. 512 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
--
2.43.0
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next parent reply other threads:[~2024-02-05 17:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240205171930.968-1-linux.amoon@gmail.com>
2024-02-05 17:19 ` Anand Moon [this message]
2024-02-27 13:03 ` [PATCHv1 1/5] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC Anand Moon
2024-02-05 17:19 ` [PATCHv1 2/5] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC Anand Moon
2024-02-06 8:54 ` Neil Armstrong
2024-02-27 13:03 ` Anand Moon
2024-02-05 17:19 ` [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS Anand Moon
2024-02-06 7:48 ` Viacheslav
2024-02-06 7:53 ` Christian Hewitt
2024-02-27 13:03 ` Anand Moon
2024-02-05 17:19 ` [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC Anand Moon
2024-02-06 9:00 ` Neil Armstrong
2024-02-06 10:15 ` Anand Moon
2024-02-06 15:01 ` neil.armstrong
2024-02-27 13:04 ` Anand Moon
2024-02-05 17:19 ` [PATCHv1 5/5] arm64: dts: amlogic: Add cache information to the Amlogic A7 SoC Anand Moon
2024-02-06 9:01 ` Neil Armstrong
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