From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: <intel-gfx@lists.freedesktop.org>,
<intel-xe@lists.freedesktop.org>,
Nirmoy Das <nirmoy.das@intel.com>,
Matthew Auld <matthew.auld@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Matt Roper <matthew.d.roper@intel.com>
Subject: Re: [PATCH v3 17/19] drm/xe/device: implement transient flush
Date: Fri, 3 May 2024 13:40:51 -0500 [thread overview]
Message-ID: <ul6vrrz3ufrmw47x27gtrkichx2sloqycf4wbl7v5h65bqkfwl@ogg63q7whwys> (raw)
In-Reply-To: <20240430172850.1881525-18-radhakrishna.sripada@intel.com>
On Tue, Apr 30, 2024 at 10:28:48AM GMT, Radhakrishna Sripada wrote:
>From: Nirmoy Das <nirmoy.das@intel.com>
>
>Display surfaces can be tagged as transient by mapping it using one of
>the various L3:XD PAT index modes on Xe2. The expectation is that KMD
>needs to request transient data flush at the start of flip sequence to
>ensure all transient data in L3 cache is flushed to memory. Add a
>routine for this which we can then call from the display code.
>
>v2: rebase(RK)
>
>Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
>Co-developed-by: Matthew Auld <matthew.auld@intel.com>
>Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
for merging this through drm-intel-next.
Lucas De Marchi
>---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++
> drivers/gpu/drm/xe/xe_device.c | 49 ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_device.h | 1 +
> 3 files changed, 53 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index 83847f2da72a..b4f1a3264e8c 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -334,6 +334,9 @@
>
> #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658)
>
>+#define XE2_TDF_CTRL XE_REG(0xb418)
>+#define TRANSIENT_FLUSH_REQUEST REG_BIT(0)
>+
> #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28)
> #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c)
> #define COMP_MOD_CTRL XE_REG_MCR(0xcf30)
>diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>index b61f8356e23e..05c28314b748 100644
>--- a/drivers/gpu/drm/xe/xe_device.c
>+++ b/drivers/gpu/drm/xe/xe_device.c
>@@ -719,6 +719,55 @@ void xe_device_wmb(struct xe_device *xe)
> xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
> }
>
>+/**
>+ * xe_device_td_flush() - Flush transient L3 cache entries
>+ * @xe: The device
>+ *
>+ * Display engine has direct access to memory and is never coherent with L3/L4
>+ * caches (or CPU caches), however KMD is responsible for specifically flushing
>+ * transient L3 GPU cache entries prior to the flip sequence to ensure scanout
>+ * can happen from such a surface without seeing corruption.
>+ *
>+ * Display surfaces can be tagged as transient by mapping it using one of the
>+ * various L3:XD PAT index modes on Xe2.
>+ *
>+ * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed
>+ * at the end of each submission via PIPE_CONTROL for compute/render, since SA
>+ * Media is not coherent with L3 and we want to support render-vs-media
>+ * usescases. For other engines like copy/blt the HW internally forces uncached
>+ * behaviour, hence why we can skip the TDF on such platforms.
>+ */
>+void xe_device_td_flush(struct xe_device *xe)
>+{
>+ struct xe_gt *gt;
>+ u8 id;
>+
>+ if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
>+ return;
>+
>+ for_each_gt(gt, xe, id) {
>+ if (xe_gt_is_media_type(gt))
>+ continue;
>+
>+ if (xe_force_wake_get(gt_to_fw(gt), XE_FW_GT))
>+ return;
>+
>+ xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
>+ /*
>+ * FIXME: We can likely do better here with our choice of
>+ * timeout. Currently we just assume the worst case, i.e. 150us,
>+ * which is believed to be sufficient to cover the worst case
>+ * scenario on current platforms if all cache entries are
>+ * transient and need to be flushed..
>+ */
>+ if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
>+ 150, NULL, false))
>+ xe_gt_err_once(gt, "TD flush timeout\n");
>+
>+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
>+ }
>+}
>+
> u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
> {
> return xe_device_has_flat_ccs(xe) ?
>diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
>index 82317580f4bf..f2a78b6a9bff 100644
>--- a/drivers/gpu/drm/xe/xe_device.h
>+++ b/drivers/gpu/drm/xe/xe_device.h
>@@ -173,5 +173,6 @@ static inline bool xe_device_wedged(struct xe_device *xe)
> }
>
> void xe_device_declare_wedged(struct xe_device *xe);
>+void xe_device_td_flush(struct xe_device *xe);
>
> #endif
>--
>2.34.1
>
next prev parent reply other threads:[~2024-05-03 18:40 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 17:28 [PATCH v3 00/19] Enable display support for Battlemage Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 01/19] drm/i915/bmg: Lane reversal requires writes to both context lanes Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 02/19] drm/i915/bmg: Define IS_BATTLEMAGE macro Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 03/19] drm/i915/xe2hpd: Initial cdclk table Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 04/19] drm/i915/bmg: Extend DG2 tc check to future Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 05/19] drm/i915/xe2hpd: Properly disable power in port A Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 06/19] drm/i915/xe2hpd: Add new C20 PHY SRAM address Radhakrishna Sripada
2024-05-03 3:24 ` Sripada, Radhakrishna
2024-04-30 17:28 ` [PATCH v3 07/19] drm/i915/xe2hpd: Add support for eDP PLL configuration Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 08/19] drm/i915/xe2hpd: update pll values in sync with Bspec Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 09/19] drm/i915/xe2hpd: Add display info Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 10/19] drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 11/19] drm/i915/xe2hpd: Add max memory bandwidth algorithm Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 12/19] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 13/19] drm/i915/bmg: BMG should re-use MTL's south display logic Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 14/19] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 15/19] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 16/19] drm/xe/gt_print: add xe_gt_err_once() Radhakrishna Sripada
2024-05-03 18:34 ` Lucas De Marchi
2024-04-30 17:28 ` [PATCH v3 17/19] drm/xe/device: implement transient flush Radhakrishna Sripada
2024-05-03 18:40 ` Lucas De Marchi [this message]
2024-04-30 17:28 ` [PATCH v3 18/19] drm/i915/display: perform " Radhakrishna Sripada
2024-04-30 17:57 ` Lucas De Marchi
2024-04-30 17:28 ` [PATCH v3 19/19] drm/xe/bmg: Enable the display support Radhakrishna Sripada
2024-04-30 17:49 ` Lucas De Marchi
2024-04-30 18:42 ` ✗ Fi.CI.CHECKPATCH: warning for Enable display support for Battlemage (rev3) Patchwork
2024-04-30 18:42 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-30 18:48 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-01 2:00 ` ✓ Fi.CI.IGT: " Patchwork
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