From: Alex Bee <knaerzche@gmail.com>
To: "Sandy Huang" <hjc@rock-chips.com>,
"Heiko Stübner" <heiko@sntech.de>,
"Andy Yan" <andy.yan@rock-chips.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, Alex Bee <knaerzche@gmail.com>
Subject: [PATCH v3 5/7] drm/rockchip: dsi: Add support for RK3128
Date: Thu, 9 May 2024 16:06:51 +0200 [thread overview]
Message-ID: <20240509140653.168591-6-knaerzche@gmail.com> (raw)
In-Reply-To: <20240509140653.168591-1-knaerzche@gmail.com>
The DesignWare MIPI DSI controller found RK3128 SoCs supports up to 4 DSI
data lanes. Similar to PX30/RK356x/RV1126 it uses an external D-PHY.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
changes since v1:
- none
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 4cc8ed8f4fbd..58a44af0e9ad 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -153,6 +153,11 @@
#define PX30_DSI_TURNDISABLE BIT(5)
#define PX30_DSI_LCDC_SEL BIT(0)
+#define RK3128_GRF_LVDS_CON0 0x0150
+#define RK3128_DSI_FORCETXSTOPMODE GENMASK(13, 10)
+#define RK3128_DSI_FORCERXMODE BIT(9)
+#define RK3128_DSI_TURNDISABLE BIT(8)
+
#define RK3288_GRF_SOC_CON6 0x025c
#define RK3288_DSI0_LCDC_SEL BIT(6)
#define RK3288_DSI1_LCDC_SEL BIT(9)
@@ -1493,6 +1498,18 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
{ /* sentinel */ }
};
+static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = {
+ {
+ .reg = 0x10110000,
+ .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,
+ .lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
+ RK3128_DSI_FORCERXMODE |
+ RK3128_DSI_FORCETXSTOPMODE),
+ .max_data_lanes = 4,
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
{
.reg = 0xff960000,
@@ -1670,6 +1687,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
{
.compatible = "rockchip,px30-mipi-dsi",
.data = &px30_chip_data,
+ }, {
+ .compatible = "rockchip,rk3128-mipi-dsi",
+ .data = &rk3128_chip_data,
}, {
.compatible = "rockchip,rk3288-mipi-dsi",
.data = &rk3288_chip_data,
--
2.43.2
next prev parent reply other threads:[~2024-05-09 14:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-09 14:06 [PATCH v3 0/7] Add DSI support for RK3128 Alex Bee
2024-05-09 14:06 ` [PATCH v3 1/7] dt-bindings: display: rockchip, dw-mipi-dsi: Document RK3128 DSI Alex Bee
2024-05-09 14:06 ` [PATCH v3 2/7] dt-bindings: clock: rk3128: Add PCLK_MIPIPHY Alex Bee
2024-05-09 14:06 ` [PATCH v3 3/7] clk: rockchip: rk3128: Export PCLK_MIPIPHY Alex Bee
2024-05-09 14:06 ` [PATCH v3 4/7] clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks Alex Bee
2024-05-09 14:06 ` Alex Bee [this message]
2024-05-09 14:06 ` [PATCH v3 6/7] ARM: dts: rockchip: Add D-PHY for RK3128 Alex Bee
2024-05-09 14:06 ` [PATCH v3 7/7] ARM: dts: rockchip: Add DSI " Alex Bee
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