From: Jan Beulich <jbeulich@suse.com>
To: Nicola Vetrini <nicola.vetrini@bugseng.com>
Cc: sstabellini@kernel.org, michal.orzel@amd.com,
xenia.ragiadakou@amd.com, ayan.kumar.halder@amd.com,
consulting@bugseng.com, bertrand.marquis@arm.com, julien@xen.org,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
xen-devel@lists.xenproject.org
Subject: Re: [XEN PATCH v3 1/7] x86/msi: address violation of MISRA C Rule 20.7 and coding style
Date: Tue, 2 Apr 2024 17:05:18 +0200 [thread overview]
Message-ID: <c958ad3e-5371-4a4e-81b5-8c313ac83258@suse.com> (raw)
In-Reply-To: <2f2c865f20d0296e623f1d65bed25c083f5dd497.1711700095.git.nicola.vetrini@bugseng.com>
On 29.03.2024 10:11, Nicola Vetrini wrote:
> MISRA C Rule 20.7 states: "Expressions resulting from the expansion
> of macro parameters shall be enclosed in parentheses". Therefore, some
> macro definitions should gain additional parentheses to ensure that all
> current and future users will be safe with respect to expansions that
> can possibly alter the semantics of the passed-in macro parameter.
>
> While at it, the style of these macros has been somewhat uniformed.
>
> No functional change.
>
> Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
> ---
> Changes in v2:
> - Make the style change more consistent
> ---
> xen/arch/x86/include/asm/msi.h | 49 +++++++++++++++++-----------------
> 1 file changed, 25 insertions(+), 24 deletions(-)
>
> diff --git a/xen/arch/x86/include/asm/msi.h b/xen/arch/x86/include/asm/msi.h
> index 997ccb87be0c..bd110c357ce4 100644
> --- a/xen/arch/x86/include/asm/msi.h
> +++ b/xen/arch/x86/include/asm/msi.h
> @@ -147,33 +147,34 @@ int msi_free_irq(struct msi_desc *entry);
> */
> #define NR_HP_RESERVED_VECTORS 20
>
> -#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
> -#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
> -#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
> -#define msi_data_reg(base, is64bit) \
> - ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
> -#define msi_mask_bits_reg(base, is64bit) \
> - ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
> +#define msi_control_reg(base) ((base) + PCI_MSI_FLAGS)
> +#define msi_lower_address_reg(base) ((base) + PCI_MSI_ADDRESS_LO)
> +#define msi_upper_address_reg(base) ((base) + PCI_MSI_ADDRESS_HI)
> +#define msi_data_reg(base, is64bit) \
> + (((is64bit) == 1) ? (base) + PCI_MSI_DATA_64 : (base) + PCI_MSI_DATA_32)
> +#define msi_mask_bits_reg(base, is64bit) \
> + (((is64bit) == 1) ? (base) + PCI_MSI_MASK_BIT \
> + : (base) + PCI_MSI_MASK_BIT - 4)
> #define msi_pending_bits_reg(base, is64bit) \
> - ((base) + PCI_MSI_MASK_BIT + ((is64bit) ? 4 : 0))
> -#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
> + ((base) + PCI_MSI_MASK_BIT + ((is64bit) ? 4 : 0))
> +#define msi_disable(control) ({ (control) &= ~PCI_MSI_FLAGS_ENABLE })
> #define multi_msi_capable(control) \
> - (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
> + (1 << (((control) & PCI_MSI_FLAGS_QMASK) >> 1))
> #define multi_msi_enable(control, num) \
> - control |= (((fls(num) - 1) << 4) & PCI_MSI_FLAGS_QSIZE);
> -#define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
> -#define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
> -#define msi_enable(control, num) multi_msi_enable(control, num); \
> - control |= PCI_MSI_FLAGS_ENABLE
> -
> -#define msix_control_reg(base) (base + PCI_MSIX_FLAGS)
> -#define msix_table_offset_reg(base) (base + PCI_MSIX_TABLE)
> -#define msix_pba_offset_reg(base) (base + PCI_MSIX_PBA)
> -#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
> -#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
> -#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
> -#define msix_unmask(address) (address & ~PCI_MSIX_VECTOR_BITMASK)
> -#define msix_mask(address) (address | PCI_MSIX_VECTOR_BITMASK)
> + ({ (control) |= (((fls(num) - 1) << 4) & PCI_MSI_FLAGS_QSIZE) })
> +#define is_64bit_address(control) (!!((control) & PCI_MSI_FLAGS_64BIT))
> +#define is_mask_bit_support(control) (!!((control) & PCI_MSI_FLAGS_MASKBIT))
> +#define msi_enable(control, num) ({ multi_msi_enable(control, num); \
> + (control) |= PCI_MSI_FLAGS_ENABLE })
Neither this nor ...
> +#define msix_control_reg(base) ((base) + PCI_MSIX_FLAGS)
> +#define msix_table_offset_reg(base) ((base) + PCI_MSIX_TABLE)
> +#define msix_pba_offset_reg(base) ((base) + PCI_MSIX_PBA)
> +#define msix_enable(control) ({ (control) |= PCI_MSIX_FLAGS_ENABLE })
> +#define msix_disable(control) ({ (control) &= ~PCI_MSIX_FLAGS_ENABLE })
... these would compile afaict, if they were used.
Once again - before fiddling with these we need to settle on which of these
we want to keep (and then also use, rather than open-coding), and which to
drop (instead of massaging).
Jan
next prev parent reply other threads:[~2024-04-02 15:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-29 9:11 [XEN PATCH v3 0/7] address violations of MISRA C Rule 20.7 Nicola Vetrini
2024-03-29 9:11 ` [XEN PATCH v3 1/7] x86/msi: address violation of MISRA C Rule 20.7 and coding style Nicola Vetrini
2024-04-02 15:05 ` Jan Beulich [this message]
2024-04-02 17:23 ` Nicola Vetrini
2024-03-29 9:11 ` [XEN PATCH v3 2/7] arm/public: address violations of MISRA C Rule 20.7 Nicola Vetrini
2024-04-05 0:11 ` Stefano Stabellini
2024-03-29 9:11 ` [XEN PATCH v3 3/7] x86/vPMU: " Nicola Vetrini
2024-04-02 14:53 ` Jan Beulich
2024-03-29 9:11 ` [XEN PATCH v3 4/7] x86/hvm: " Nicola Vetrini
2024-04-02 14:55 ` Jan Beulich
2024-03-29 9:11 ` [XEN PATCH v3 5/7] automation/eclair: add deviations for " Nicola Vetrini
2024-04-05 0:13 ` Stefano Stabellini
2024-04-05 0:27 ` Stefano Stabellini
2024-03-29 9:11 ` [XEN PATCH v3 6/7] xen/mm: address violations of MISRA C " Nicola Vetrini
2024-04-02 14:56 ` Jan Beulich
2024-03-29 9:11 ` [XEN PATCH v3 7/7] x86/amd: " Nicola Vetrini
2024-04-02 14:57 ` Jan Beulich
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