Re: [PATCH] drm/stm: dsi: relax mode_valid clock tolerance

From: Robert Foss <rfoss@kernel.org>
To: Sean Nyekjaer <sean@geanix.com>
Cc: Yannick Fertre <yannick.fertre@foss.st.com>,
	 Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>,
	 Philippe Cornu <philippe.cornu@foss.st.com>,
	 Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	 Thomas Zimmermann <tzimmermann@suse.de>,
	David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
	 Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	 Antonio Borneo <antonio.borneo@foss.st.com>,
	dri-devel@lists.freedesktop.org,
	 linux-stm32@st-md-mailman.stormreply.com,
	 linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] drm/stm: dsi: relax mode_valid clock tolerance
Date: Tue, 23 Apr 2024 15:32:15 +0200	[thread overview]
Message-ID: <CAN6tsi40-gGgG3Bw-rS4TZBO+=JthWkPh-XqErGvkHdvhqx6tA@mail.gmail.com> (raw)
In-Reply-To: <lkrxoqhcitmvjvzslhx6mrdjaa6lpxtpmdjt7wwollm6z4h65q@jk5esjje6ppy>

On Mon, Apr 22, 2024 at 4:06 PM Sean Nyekjaer <sean@geanix.com> wrote:
>
> On Fri, Mar 22, 2024 at 11:47:31AM +0100, Sean Nyekjaer wrote:
> > When using the DSI interface via DSI2LVDS bridge, it seems a bit harsh
> > to reguire the requested and the actual px clock to be within
> > 50Hz. A typical LVDS display requires the px clock to be within +-10%.
> >
> > In case for HDMI .5% tolerance is required.
> >
> > Fixes: e01356d18273 ("drm/stm: dsi: provide the implementation of mode_valid()")
> > Signed-off-by: Sean Nyekjaer <sean@geanix.com>
> > ---
> Any feedback on this?
>
> >  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 7 +++----
> >  1 file changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> > index d5f8c923d7bc..97936b0ef702 100644
> > --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> > +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> > @@ -322,8 +322,6 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> >       return 0;
> >  }
> >
> > -#define CLK_TOLERANCE_HZ 50
> > -
> >  static enum drm_mode_status
> >  dw_mipi_dsi_stm_mode_valid(void *priv_data,
> >                          const struct drm_display_mode *mode,
> > @@ -375,9 +373,10 @@ dw_mipi_dsi_stm_mode_valid(void *priv_data,
> >               /*
> >                * Filter modes according to the clock value, particularly useful for
> >                * hdmi modes that require precise pixel clocks.
> > +              * Check that px_clock is within .5% tolerance.
> >                */
> > -             if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ ||
> > -                 px_clock_hz > target_px_clock_hz + CLK_TOLERANCE_HZ)
> > +             if (px_clock_hz < mult_frac(target_px_clock_hz, 995, 1000) ||
> > +                 px_clock_hz > mult_frac(target_px_clock_hz, 1005, 1000))
> >                       return MODE_CLOCK_RANGE;
> >
> >               /* sync packets are codes as DSI short packets (4 bytes) */
> > --
> > 2.44.0
> >
>

Reviewed-by: Robert Foss <rfoss@kernel.org>