From: Tony Luck <tony.luck@intel.com>
To: Borislav Petkov <bp@alien8.de>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>
Cc: Tony Luck <tony.luck@intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
linux-kernel@vger.kernel.org, patches@lists.linux.dev
Subject: [PATCH v4 71/71] x86/cpu/vfm: Delete all the *_FAM6_ CPU #defines
Date: Wed, 24 Apr 2024 11:15:53 -0700 [thread overview]
Message-ID: <20240424181554.42524-1-tony.luck@intel.com> (raw)
In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com>
All code has been converted to use the vendor/family/model versions.
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/include/asm/intel-family.h | 85 +----------------------------
1 file changed, 2 insertions(+), 83 deletions(-)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index f81a851c46dc..f7289094a483 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -10,7 +10,7 @@
* that group keep the CPUID for the variants sorted by model number.
*
* The defined symbol names have the following form:
- * INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
+ * INTEL_{OPTFAMILY}_{MICROARCH}{OPTDIFF}
* where:
* OPTFAMILY Describes the family of CPUs that this belongs to. Default
* is assumed to be "_CORE" (and should be omitted). Other values
@@ -42,215 +42,134 @@
#define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model)
-/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
-#define INTEL_FAM6_ANY X86_MODEL_ANY
-/* Wildcard match for FAM6 so X86_MATCH_VFM(ANY) works */
+/* Wildcard match so X86_MATCH_VFM(ANY) works */
#define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY)
-#define INTEL_FAM6_CORE_YONAH 0x0E
#define INTEL_CORE_YONAH IFM(6, 0x0E)
-#define INTEL_FAM6_CORE2_MEROM 0x0F
#define INTEL_CORE2_MEROM IFM(6, 0x0F)
-#define INTEL_FAM6_CORE2_MEROM_L 0x16
#define INTEL_CORE2_MEROM_L IFM(6, 0x16)
-#define INTEL_FAM6_CORE2_PENRYN 0x17
#define INTEL_CORE2_PENRYN IFM(6, 0x17)
-#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
#define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D)
-#define INTEL_FAM6_NEHALEM 0x1E
#define INTEL_NEHALEM IFM(6, 0x1E)
-#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
#define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */
-#define INTEL_FAM6_NEHALEM_EP 0x1A
#define INTEL_NEHALEM_EP IFM(6, 0x1A)
-#define INTEL_FAM6_NEHALEM_EX 0x2E
#define INTEL_NEHALEM_EX IFM(6, 0x2E)
-#define INTEL_FAM6_WESTMERE 0x25
#define INTEL_WESTMERE IFM(6, 0x25)
-#define INTEL_FAM6_WESTMERE_EP 0x2C
#define INTEL_WESTMERE_EP IFM(6, 0x2C)
-#define INTEL_FAM6_WESTMERE_EX 0x2F
#define INTEL_WESTMERE_EX IFM(6, 0x2F)
-#define INTEL_FAM6_SANDYBRIDGE 0x2A
#define INTEL_SANDYBRIDGE IFM(6, 0x2A)
-#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
#define INTEL_SANDYBRIDGE_X IFM(6, 0x2D)
-#define INTEL_FAM6_IVYBRIDGE 0x3A
#define INTEL_IVYBRIDGE IFM(6, 0x3A)
-#define INTEL_FAM6_IVYBRIDGE_X 0x3E
#define INTEL_IVYBRIDGE_X IFM(6, 0x3E)
-#define INTEL_FAM6_HASWELL 0x3C
#define INTEL_HASWELL IFM(6, 0x3C)
-#define INTEL_FAM6_HASWELL_X 0x3F
#define INTEL_HASWELL_X IFM(6, 0x3F)
-#define INTEL_FAM6_HASWELL_L 0x45
#define INTEL_HASWELL_L IFM(6, 0x45)
-#define INTEL_FAM6_HASWELL_G 0x46
#define INTEL_HASWELL_G IFM(6, 0x46)
-#define INTEL_FAM6_BROADWELL 0x3D
#define INTEL_BROADWELL IFM(6, 0x3D)
-#define INTEL_FAM6_BROADWELL_G 0x47
#define INTEL_BROADWELL_G IFM(6, 0x47)
-#define INTEL_FAM6_BROADWELL_X 0x4F
#define INTEL_BROADWELL_X IFM(6, 0x4F)
-#define INTEL_FAM6_BROADWELL_D 0x56
#define INTEL_BROADWELL_D IFM(6, 0x56)
-#define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */
#define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */
-#define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */
#define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */
-#define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */
#define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */
/* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */
/* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */
-#define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */
#define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */
/* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */
/* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */
/* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */
-#define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */
#define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */
/* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */
-#define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */
#define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */
-#define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */
#define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */
-#define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */
#define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */
-#define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */
#define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */
-#define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */
#define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */
-#define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */
#define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */
-#define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */
#define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */
-#define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */
#define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */
-#define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */
#define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */
-#define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */
#define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */
-#define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */
#define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */
-#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */
#define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */
-#define INTEL_FAM6_EMERALDRAPIDS_X 0xCF
#define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF)
-#define INTEL_FAM6_GRANITERAPIDS_X 0xAD
#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD)
-#define INTEL_FAM6_GRANITERAPIDS_D 0xAE
#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
/* "Hybrid" Processors (P-Core/E-Core) */
-#define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */
#define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */
-#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */
#define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */
-#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */
#define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */
-#define INTEL_FAM6_RAPTORLAKE 0xB7 /* Raptor Cove / Enhanced Gracemont */
#define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */
-#define INTEL_FAM6_RAPTORLAKE_P 0xBA
#define INTEL_RAPTORLAKE_P IFM(6, 0xBA)
-#define INTEL_FAM6_RAPTORLAKE_S 0xBF
#define INTEL_RAPTORLAKE_S IFM(6, 0xBF)
-#define INTEL_FAM6_METEORLAKE 0xAC
#define INTEL_METEORLAKE IFM(6, 0xAC)
-#define INTEL_FAM6_METEORLAKE_L 0xAA
#define INTEL_METEORLAKE_L IFM(6, 0xAA)
-#define INTEL_FAM6_ARROWLAKE_H 0xC5
#define INTEL_ARROWLAKE_H IFM(6, 0xC5)
-#define INTEL_FAM6_ARROWLAKE 0xC6
#define INTEL_ARROWLAKE IFM(6, 0xC6)
-#define INTEL_FAM6_ARROWLAKE_U 0xB5
#define INTEL_ARROWLAKE_U IFM(6, 0xB5)
-#define INTEL_FAM6_LUNARLAKE_M 0xBD
#define INTEL_LUNARLAKE_M IFM(6, 0xBD)
/* "Small Core" Processors (Atom/E-Core) */
-#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
#define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */
-#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
#define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */
-#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
#define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */
-#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
#define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */
-#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
#define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */
-#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
#define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */
-#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
#define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */
-#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
#define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */
-#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
#define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */
-#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
#define INTEL_ATOM_AIRMONT_MID IFM(6, 0x5A) /* Moorefield */
-#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
#define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */
-#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
#define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */
-#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
#define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */
/* Note: the micro-architecture is "Goldmont Plus" */
-#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
#define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */
-#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
#define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */
-#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
#define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */
-#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
#define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */
-#define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */
#define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */
-#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
#define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */
-#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */
#define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */
-#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */
#define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */
/* Xeon Phi */
-#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
#define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */
-#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
#define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */
/* Family 5 */
--
2.44.0
next prev parent reply other threads:[~2024-04-24 18:15 UTC|newest]
Thread overview: 109+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-24 18:12 [PATCH v4 00/71] New Intel CPUID families Tony Luck
2024-04-24 18:14 ` [PATCH v4 01/71] tpm: Switch to new Intel CPU model defines Tony Luck
2024-04-25 4:48 ` Jarkko Sakkinen
2024-04-25 4:50 ` Jarkko Sakkinen
2024-04-24 18:14 ` [PATCH v4 02/71] platform/x86/intel/ifs: " Tony Luck
2024-04-29 3:19 ` Kuppuswamy Sathyanarayanan
2024-04-24 18:14 ` [PATCH v4 03/71] KVM: x86/pmu: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 04/71] KVM: VMX: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 05/71] ACPI: LPSS: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 06/71] ACPI: x86: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 07/71] cpufreq: intel_pstate: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 08/71] cpufreq: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 09/71] intel_idle: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 10/71] PCI: PM: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 11/71] powercap: intel_rapl: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 12/71] " Tony Luck
2024-04-24 18:14 ` [PATCH v4 13/71] ASoC: Intel: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 14/71] thermal: intel: intel_tcc_cooling: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 15/71] tools/power/turbostat: " Tony Luck
2024-04-24 18:14 ` [PATCH v4 17/71] crypto: x86/twofish - " Tony Luck
2024-04-24 18:14 ` [PATCH v4 16/71] crypto: x86/poly1305 " Tony Luck
2024-05-31 9:37 ` Herbert Xu
2024-04-24 18:14 ` [PATCH v4 18/71] perf/x86/intel/cstate: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 20/71] perf/x86/intel/pt: " Tony Luck
2024-04-25 15:58 ` Dave Hansen
2024-04-24 18:15 ` [PATCH v4 19/71] perf/x86/lbr: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 21/71] perf/x86/intel/uncore: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 22/71] " Tony Luck
2024-04-24 18:15 ` [PATCH v4 24/71] perf/x86/msr: " Tony Luck
2024-04-25 15:49 ` Dave Hansen
2024-04-25 16:43 ` Luck, Tony
2024-04-25 16:47 ` Dave Hansen
2024-04-25 16:54 ` Luck, Tony
2024-04-24 18:15 ` [PATCH v4 23/71] perf/x86/intel/uncore: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 25/71] x86/apic: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 26/71] x86/aperfmperf: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 27/71] x86/bugs: " Tony Luck
2024-04-24 20:55 ` Josh Poimboeuf
2024-04-25 10:52 ` [tip: x86/cpu] " tip-bot2 for Tony Luck
2024-04-24 18:15 ` [PATCH v4 28/71] " Tony Luck
2024-04-24 21:09 ` Josh Poimboeuf
2024-04-25 10:52 ` [tip: x86/cpu] " tip-bot2 for Tony Luck
2024-04-24 18:15 ` [PATCH v4 29/71] x86/cpu/intel: " Tony Luck
2024-04-25 10:46 ` Borislav Petkov
2024-04-25 16:29 ` Luck, Tony
2024-04-28 18:27 ` Borislav Petkov
2024-04-24 18:15 ` [PATCH v4 30/71] x86/cpu/intel_epb: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 32/71] x86/mce: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 31/71] x86/cpu: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 33/71] x86/mce: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 35/71] x86/microcode/intel: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 34/71] x86/mce: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 37/71] x86/resctrl: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 36/71] " Tony Luck
2024-04-24 18:15 ` [PATCH v4 38/71] x86/cpu/: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 39/71] x86/tsc: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 41/71] x86/mm: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 40/71] x86/tsc_msr: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 42/71] x86/PCI: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 43/71] x86/virt/tdx: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 44/71] perf/x86/intel: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 45/71] x86/platform/intel-mid: " Tony Luck
2024-04-24 19:28 ` Andy Shevchenko
2024-04-24 18:15 ` [PATCH v4 46/71] x86/platform/atom: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 47/71] x86/cpu: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 48/71] x86/boot: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 49/71] EDAC/i10nm: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 50/71] EDAC, pnd2: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 51/71] EDAC/sb_edac: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 52/71] EDAC/skx: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 53/71] extcon: axp288: " Tony Luck
2024-05-08 15:21 ` Chanwoo Choi
2024-04-24 18:15 ` [PATCH v4 54/71] peci: cpu: " Tony Luck
2024-04-24 18:15 ` Tony Luck
2024-04-24 18:15 ` [PATCH v4 55/71] hwmon: (peci/cputemp) " Tony Luck
2024-04-24 20:00 ` Guenter Roeck
2024-04-24 20:25 ` Luck, Tony
2024-04-25 19:58 ` Tony Luck
2024-04-26 1:07 ` Winiarska, Iwona
2024-04-26 15:56 ` Luck, Tony
2024-04-24 18:15 ` [PATCH v4 56/71] platform/x86: intel_ips: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 57/71] platform/x86/intel/pmc: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 58/71] platform/x86/intel: pmc: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 59/71] platform/x86: intel_scu_wdt: " Tony Luck
2024-04-29 3:19 ` Kuppuswamy Sathyanarayanan
2024-04-24 18:15 ` [PATCH v4 60/71] platform/x86: ISST: " Tony Luck
2024-04-25 12:32 ` srinivas pandruvada
2024-04-25 16:34 ` Luck, Tony
2024-04-24 18:15 ` [PATCH v4 61/71] platform/x86: intel_speed_select_if: " Tony Luck
2024-04-25 12:33 ` srinivas pandruvada
2024-04-24 18:15 ` [PATCH v4 62/71] platform/x86: intel_telemetry: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 63/71] platform/x86: intel: telemetry: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 64/71] platform/x86: intel_turbo_max_3: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 65/71] platform/x86: intel-uncore-freq: " Tony Luck
2024-04-25 12:34 ` srinivas pandruvada
2024-04-24 18:15 ` [PATCH v4 66/71] platform/x86: p2sb: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 67/71] media: atomisp: " Tony Luck
2024-04-24 19:31 ` Andy Shevchenko
2024-04-24 18:15 ` [PATCH v4 68/71] ASoC: Intel: avs: es8336: " Tony Luck
2024-04-24 23:58 ` Mark Brown
2024-04-25 0:12 ` Luck, Tony
2024-04-25 0:58 ` Mark Brown
2024-04-25 7:39 ` Amadeusz Sławiński
2024-04-24 18:15 ` [PATCH v4 69/71] perf/x86/rapl: " Tony Luck
2024-04-24 18:15 ` [PATCH v4 70/71] x86/cpu/vfm: Delete X86_MATCH_INTEL_FAM6_MODEL[_STEPPING]() macros Tony Luck
2024-04-24 18:15 ` Tony Luck [this message]
2024-04-24 18:39 ` [PATCH v4 00/71] New Intel CPUID families Dave Hansen
2024-04-24 18:57 ` Luck, Tony
2024-04-29 8:08 ` Hans de Goede
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