From: Vladimir Oltean <olteanv@gmail.com> To: Matthew Hagan <mnhagan88@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com>, Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>, soc@kernel.org, Ray Jui <rjui@broadcom.com>, Scott Branden <sbranden@broadcom.com>, bcm-kernel-feedback-list@broadcom.com, Sam Ravnborg <sam@ravnborg.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Viresh Kumar <viresh.kumar@linaro.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65 Date: Fri, 11 Jun 2021 23:30:31 +0300 [thread overview] Message-ID: <20210611203031.fj3g32o7kgupgzjy@skbuf> (raw) In-Reply-To: <20210610232727.1383117-4-mnhagan88@gmail.com> On Fri, Jun 11, 2021 at 12:27:15AM +0100, Matthew Hagan wrote: > These bindings are required for all Meraki MX64/MX65 devices. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > --- > .../dts/bcm958625-meraki-mx6x-common.dtsi | 148 ++++++++++++++++++ > 1 file changed, 148 insertions(+) > create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi > > diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi > new file mode 100644 > index 000000000000..47a30dedf7b3 > --- /dev/null > +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi > @@ -0,0 +1,148 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > +/* > + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. > + * > + * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com> > + */ > + > +#include "bcm-nsp.dtsi" > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x60000000 0x80000000>; > + }; > + > + pwm-leds { > + compatible = "pwm-leds"; > + > + red { > + label = "red:led"; > + pwms = <&pwm 1 50000>; > + }; > + > + green { > + label = "green:led"; > + pwms = <&pwm 2 50000>; > + }; > + > + blue { > + label = "blue:led"; > + pwms = <&pwm 3 50000>; > + }; > + }; > +}; > + > +&L2 { > + arm,io-coherent; > + prefetch-data = <1>; > + prefetch-instr = <1>; > +}; It is common practice to sort labels alphabetically and nodes by unit address. > + > +&uart0 { > + clock-frequency = <62500000>; > + status = "okay"; > +}; > + > +&i2c0 { > + status = "okay"; > + at24@50 { > + compatible = "atmel,24c64"; > + pagesize = <32>; > + reg = <0x50>; > + }; > +}; > + > +&amac2 { > + status = "okay"; > +}; > + > +&nand { > + nandcs@0 { > + compatible = "brcm,nandcs"; > + reg = <0>; > + nand-on-flash-bbt; > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + nand-ecc-strength = <24>; > + nand-ecc-step-size = <1024>; > + > + brcm,nand-oob-sector-size = <27>; > + > + partition@0 { > + label = "u-boot"; > + reg = <0x0 0x80000>; > + read-only; > + }; > + > + partition@80000 { > + label = "shmoo"; > + reg = <0x80000 0x80000>; > + read-only; > + }; > + > + partition@100000 { > + label = "bootkernel1"; > + reg = <0x100000 0x300000>; > + }; > + > + partition@400000 { > + label = "senao_nvram"; > + reg = <0x400000 0x100000>; > + }; > + > + partition@500000 { > + label = "bootkernel2"; > + reg = <0x500000 0x300000>; > + }; > + > + partition@800000 { > + label = "ubi"; > + reg = <0x800000 0x3f700000>; > + }; > + }; > +}; > + > +&qspi { > + status = "disabled"; > +}; > + > +&ehci0 { > + status = "okay"; > +}; > + > +&ohci0 { > + status = "okay"; > +}; > + > +&pwm { > + status = "okay"; > + #pwm-cells = <2>; What is the reason for overriding this to 2? > + chan0 { > + channel = <1>; > + active_low = <1>; > + }; Bad indentation for this bracket. > + chan1 { > + channel = <2>; > + active_low = <1>; > + }; > + chan2 { > + channel = <3>; > + active_low = <1>; > + }; > +}; > + > +&ccbtimer1 { > + status = "disabled"; > +}; > + > +&sata_phy { > + status = "disabled"; > +}; It is common practice to disable these in the common SoC dtsi and let individual boards enable them as necessary, instead of the opposite. > -- > 2.26.3 >
WARNING: multiple messages have this Message-ID (diff)
From: Vladimir Oltean <olteanv@gmail.com> To: Matthew Hagan <mnhagan88@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com>, Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>, soc@kernel.org, Ray Jui <rjui@broadcom.com>, Scott Branden <sbranden@broadcom.com>, bcm-kernel-feedback-list@broadcom.com, Sam Ravnborg <sam@ravnborg.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Viresh Kumar <viresh.kumar@linaro.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65 Date: Fri, 11 Jun 2021 23:30:31 +0300 [thread overview] Message-ID: <20210611203031.fj3g32o7kgupgzjy@skbuf> (raw) In-Reply-To: <20210610232727.1383117-4-mnhagan88@gmail.com> On Fri, Jun 11, 2021 at 12:27:15AM +0100, Matthew Hagan wrote: > These bindings are required for all Meraki MX64/MX65 devices. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > --- > .../dts/bcm958625-meraki-mx6x-common.dtsi | 148 ++++++++++++++++++ > 1 file changed, 148 insertions(+) > create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi > > diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi > new file mode 100644 > index 000000000000..47a30dedf7b3 > --- /dev/null > +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi > @@ -0,0 +1,148 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > +/* > + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. > + * > + * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com> > + */ > + > +#include "bcm-nsp.dtsi" > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x60000000 0x80000000>; > + }; > + > + pwm-leds { > + compatible = "pwm-leds"; > + > + red { > + label = "red:led"; > + pwms = <&pwm 1 50000>; > + }; > + > + green { > + label = "green:led"; > + pwms = <&pwm 2 50000>; > + }; > + > + blue { > + label = "blue:led"; > + pwms = <&pwm 3 50000>; > + }; > + }; > +}; > + > +&L2 { > + arm,io-coherent; > + prefetch-data = <1>; > + prefetch-instr = <1>; > +}; It is common practice to sort labels alphabetically and nodes by unit address. > + > +&uart0 { > + clock-frequency = <62500000>; > + status = "okay"; > +}; > + > +&i2c0 { > + status = "okay"; > + at24@50 { > + compatible = "atmel,24c64"; > + pagesize = <32>; > + reg = <0x50>; > + }; > +}; > + > +&amac2 { > + status = "okay"; > +}; > + > +&nand { > + nandcs@0 { > + compatible = "brcm,nandcs"; > + reg = <0>; > + nand-on-flash-bbt; > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + nand-ecc-strength = <24>; > + nand-ecc-step-size = <1024>; > + > + brcm,nand-oob-sector-size = <27>; > + > + partition@0 { > + label = "u-boot"; > + reg = <0x0 0x80000>; > + read-only; > + }; > + > + partition@80000 { > + label = "shmoo"; > + reg = <0x80000 0x80000>; > + read-only; > + }; > + > + partition@100000 { > + label = "bootkernel1"; > + reg = <0x100000 0x300000>; > + }; > + > + partition@400000 { > + label = "senao_nvram"; > + reg = <0x400000 0x100000>; > + }; > + > + partition@500000 { > + label = "bootkernel2"; > + reg = <0x500000 0x300000>; > + }; > + > + partition@800000 { > + label = "ubi"; > + reg = <0x800000 0x3f700000>; > + }; > + }; > +}; > + > +&qspi { > + status = "disabled"; > +}; > + > +&ehci0 { > + status = "okay"; > +}; > + > +&ohci0 { > + status = "okay"; > +}; > + > +&pwm { > + status = "okay"; > + #pwm-cells = <2>; What is the reason for overriding this to 2? > + chan0 { > + channel = <1>; > + active_low = <1>; > + }; Bad indentation for this bracket. > + chan1 { > + channel = <2>; > + active_low = <1>; > + }; > + chan2 { > + channel = <3>; > + active_low = <1>; > + }; > +}; > + > +&ccbtimer1 { > + status = "disabled"; > +}; > + > +&sata_phy { > + status = "disabled"; > +}; It is common practice to disable these in the common SoC dtsi and let individual boards enable them as necessary, instead of the opposite. > -- > 2.26.3 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-11 20:31 UTC|newest] Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-10 23:27 [PATCH v2 0/5] ARM: dts: NSP: add Meraki MX64/MX65 Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-10 23:27 ` [PATCH v2 1/5] dt-bindings: arm: bcm: " Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-11 19:46 ` Vladimir Oltean 2021-06-11 19:46 ` Vladimir Oltean 2021-06-12 9:21 ` Matthew Hagan 2021-06-12 9:21 ` Matthew Hagan 2021-06-12 15:07 ` Vladimir Oltean 2021-06-12 15:07 ` Vladimir Oltean 2021-06-10 23:27 ` [PATCH v2 2/5] ARM: dts: NSP: Add Meraki MX64/MX65 to Makefile Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-11 20:24 ` Vladimir Oltean 2021-06-11 20:24 ` Vladimir Oltean 2021-06-12 9:23 ` Matthew Hagan 2021-06-12 9:23 ` Matthew Hagan 2021-06-10 23:27 ` [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65 Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-11 20:30 ` Vladimir Oltean [this message] 2021-06-11 20:30 ` Vladimir Oltean 2021-06-12 23:14 ` Matthew Hagan 2021-06-12 23:14 ` Matthew Hagan 2021-06-13 2:03 ` Florian Fainelli 2021-06-13 2:03 ` Florian Fainelli 2021-06-10 23:27 ` [PATCH v2 4/5] ARM: dts: NSP: Add DT files for Meraki MX64 series Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-10 23:27 ` [PATCH v2 5/5] ARM: dts: NSP: Add DT files for Meraki MX65 series Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-10 23:27 ` Matthew Hagan 2021-06-11 19:02 ` Matthew Hagan 2021-06-11 19:02 ` Matthew Hagan 2021-06-11 19:02 ` Matthew Hagan 2021-06-11 20:48 ` Vladimir Oltean 2021-06-11 20:48 ` Vladimir Oltean
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