From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 7/9] drm/i915/fbc: Extract intel_fbc_stolen_end()
Date: Thu, 10 Jun 2021 21:32:35 +0300 [thread overview]
Message-ID: <20210610183237.3920-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210610183237.3920-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Declutter find_compression_limit() a bit by extracting
intel_fbc_stolen_end().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 31ac1163f55b..6415f2cfd1ac 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -423,13 +423,8 @@ static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
return BIT_ULL(32);
}
-static int find_compression_limit(struct drm_i915_private *dev_priv,
- unsigned int size,
- unsigned int fb_cpp)
+static u64 intel_fbc_stolen_end(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
- int compression_limit = 1;
- int ret;
u64 end;
/* The FBC hardware for BDW/SKL doesn't have access to the stolen
@@ -442,7 +437,17 @@ static int find_compression_limit(struct drm_i915_private *dev_priv,
else
end = U64_MAX;
- end = min(end, intel_fbc_cfb_base_max(dev_priv));
+ return min(end, intel_fbc_cfb_base_max(dev_priv));
+}
+
+static int find_compression_limit(struct drm_i915_private *dev_priv,
+ unsigned int size,
+ unsigned int fb_cpp)
+{
+ struct intel_fbc *fbc = &dev_priv->fbc;
+ u64 end = intel_fbc_stolen_end(dev_priv);
+ int compression_limit = 1;
+ int ret;
/* HACK: This code depends on what we will do in *_enable_fbc. If that
* code changes, this code needs to change as well.
--
2.31.1
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next prev parent reply other threads:[~2021-06-10 18:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 18:32 [Intel-gfx] [PATCH 0/9] drm/i915/fbc: Clean up cfb allocation code Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 1/9] drm/i915/fbc: s/threshold/limit/ Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 2/9] drm/i915/fbc: Extract intel_fbc_program_cfb() Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 3/9] drm/i915/fbc: Embed the compressed_llb node Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 4/9] drm/i915/fbc: Don't pass around the mm node Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 5/9] drm/i915/fbc: Handle 16bpp compression limit better Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 6/9] drm/i915/fbc: Introduce g4x_dpfc_ctl_limit() Ville Syrjala
2021-06-10 18:32 ` Ville Syrjala [this message]
2021-06-10 18:32 ` [Intel-gfx] [PATCH 8/9] drm/i915/fbc: Make the cfb allocation loop a bit more legible Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 9/9] drm/i915/fbc: Allocate llb before cfb Ville Syrjala
2021-06-18 21:07 ` Souza, Jose
2021-06-10 18:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Clean up cfb allocation code Patchwork
2021-06-10 19:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-10 22:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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