From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/9] drm/i915/fbc: Extract intel_fbc_program_cfb()
Date: Thu, 10 Jun 2021 21:32:30 +0300 [thread overview]
Message-ID: <20210610183237.3920-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210610183237.3920-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extract the CFB (+LLB) programming into a separate function.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 46 ++++++++++++++----------
1 file changed, 28 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 715f5c60d9c5..3b0e3e913ef9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -506,13 +506,7 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
fbc->limit = ret;
- if (DISPLAY_VER(dev_priv) >= 5)
- intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
- fbc->compressed_fb.start);
- else if (IS_GM45(dev_priv)) {
- intel_de_write(dev_priv, DPFC_CB_BASE,
- fbc->compressed_fb.start);
- } else {
+ if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
if (!compressed_llb)
goto err_fb;
@@ -523,17 +517,6 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
goto err_fb;
fbc->compressed_llb = compressed_llb;
-
- GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
- fbc->compressed_fb.start,
- U32_MAX));
- GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
- fbc->compressed_llb->start,
- U32_MAX));
- intel_de_write(dev_priv, FBC_CFB_BASE,
- dev_priv->dsm.start + fbc->compressed_fb.start);
- intel_de_write(dev_priv, FBC_LL_BASE,
- dev_priv->dsm.start + compressed_llb->start);
}
drm_dbg_kms(&dev_priv->drm,
@@ -551,6 +534,31 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
return -ENOSPC;
}
+static void intel_fbc_program_cfb(struct drm_i915_private *dev_priv)
+{
+ struct intel_fbc *fbc = &dev_priv->fbc;
+
+ if (DISPLAY_VER(dev_priv) >= 5) {
+ intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
+ fbc->compressed_fb.start);
+ } else if (IS_GM45(dev_priv)) {
+ intel_de_write(dev_priv, DPFC_CB_BASE,
+ fbc->compressed_fb.start);
+ } else {
+ GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
+ fbc->compressed_fb.start,
+ U32_MAX));
+ GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
+ fbc->compressed_llb->start,
+ U32_MAX));
+
+ intel_de_write(dev_priv, FBC_CFB_BASE,
+ dev_priv->dsm.start + fbc->compressed_fb.start);
+ intel_de_write(dev_priv, FBC_LL_BASE,
+ dev_priv->dsm.start + fbc->compressed_llb->start);
+ }
+}
+
static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
{
struct intel_fbc *fbc = &dev_priv->fbc;
@@ -1302,6 +1310,8 @@ void intel_fbc_enable(struct intel_atomic_state *state,
fbc->no_fbc_reason = "FBC enabled but not active yet\n";
fbc->crtc = crtc;
+
+ intel_fbc_program_cfb(dev_priv);
out:
mutex_unlock(&fbc->lock);
}
--
2.31.1
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next prev parent reply other threads:[~2021-06-10 18:32 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 18:32 [Intel-gfx] [PATCH 0/9] drm/i915/fbc: Clean up cfb allocation code Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 1/9] drm/i915/fbc: s/threshold/limit/ Ville Syrjala
2021-06-10 18:32 ` Ville Syrjala [this message]
2021-06-10 18:32 ` [Intel-gfx] [PATCH 3/9] drm/i915/fbc: Embed the compressed_llb node Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 4/9] drm/i915/fbc: Don't pass around the mm node Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 5/9] drm/i915/fbc: Handle 16bpp compression limit better Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 6/9] drm/i915/fbc: Introduce g4x_dpfc_ctl_limit() Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 7/9] drm/i915/fbc: Extract intel_fbc_stolen_end() Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 8/9] drm/i915/fbc: Make the cfb allocation loop a bit more legible Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 9/9] drm/i915/fbc: Allocate llb before cfb Ville Syrjala
2021-06-18 21:07 ` Souza, Jose
2021-06-10 18:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Clean up cfb allocation code Patchwork
2021-06-10 19:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-10 22:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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