From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v7 20/27] tcg/tci: Implement clz, ctz, ctpop
Date: Tue, 1 Jun 2021 08:00:59 -0700 [thread overview]
Message-ID: <20210601150106.12761-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210601150106.12761-1-richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 12 +++++------
tcg/tci.c | 44 ++++++++++++++++++++++++++++++++++++++++
tcg/tci/tcg-target.c.inc | 9 ++++++++
3 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 60b67b196b..59859bd8a6 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -75,9 +75,9 @@
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
-#define TCG_TARGET_HAS_clz_i32 0
-#define TCG_TARGET_HAS_ctz_i32 0
-#define TCG_TARGET_HAS_ctpop_i32 0
+#define TCG_TARGET_HAS_clz_i32 1
+#define TCG_TARGET_HAS_ctz_i32 1
+#define TCG_TARGET_HAS_ctpop_i32 1
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 1
@@ -112,9 +112,9 @@
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1
-#define TCG_TARGET_HAS_clz_i64 0
-#define TCG_TARGET_HAS_ctz_i64 0
-#define TCG_TARGET_HAS_ctpop_i64 0
+#define TCG_TARGET_HAS_clz_i64 1
+#define TCG_TARGET_HAS_ctz_i64 1
+#define TCG_TARGET_HAS_ctpop_i64 1
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 1
diff --git a/tcg/tci.c b/tcg/tci.c
index 22ee32bc24..1e2737e079 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -587,6 +587,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
break;
+#if TCG_TARGET_HAS_clz_i32
+ case INDEX_op_clz_i32:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ tmp32 = regs[r1];
+ regs[r0] = tmp32 ? clz32(tmp32) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctz_i32
+ case INDEX_op_ctz_i32:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ tmp32 = regs[r1];
+ regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctpop_i32
+ case INDEX_op_ctpop_i32:
+ tci_args_rr(insn, &r0, &r1);
+ regs[r0] = ctpop32(regs[r1]);
+ break;
+#endif
/* Shift/rotate operations (32 bit). */
@@ -739,6 +759,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
break;
+#if TCG_TARGET_HAS_clz_i64
+ case INDEX_op_clz_i64:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctz_i64
+ case INDEX_op_ctz_i64:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctpop_i64
+ case INDEX_op_ctpop_i64:
+ tci_args_rr(insn, &r0, &r1);
+ regs[r0] = ctpop64(regs[r1]);
+ break;
+#endif
/* Shift/rotate operations (64 bit). */
@@ -1165,6 +1203,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_not_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_ctpop_i64:
tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s, %s",
op_name, str_r(r0), str_r(r1));
@@ -1210,6 +1250,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_ctz_i64:
tci_args_rrr(insn, &r0, &r1, &r2);
info->fprintf_func(info->stream, "%-12s %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2));
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 677ae2dceb..748bc13d4e 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -67,6 +67,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_ctpop_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
@@ -122,6 +124,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_setcond_i64:
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_ctz_i64:
return C_O1_I2(r, r, r);
case INDEX_op_brcond_i32:
@@ -655,6 +661,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
+ CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */
+ CASE_32_64(ctz) /* Optional (TCG_TARGET_HAS_ctz_*). */
tcg_out_op_rrr(s, opc, args[0], args[1], args[2]);
break;
@@ -703,6 +711,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
+ CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
--
2.25.1
next prev parent reply other threads:[~2021-06-01 15:22 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
2021-06-01 15:00 ` [PATCH v7 01/27] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode Richard Henderson
2021-06-01 15:00 ` [PATCH v7 02/27] tcg: Add tcg_call_flags Richard Henderson
2021-06-01 15:00 ` [PATCH v7 03/27] accel/tcg/plugin-gen: Drop inline markers Richard Henderson
2021-06-01 15:00 ` [PATCH v7 04/27] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Richard Henderson
2021-06-02 9:22 ` Alex Bennée
2021-06-02 16:02 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 05/27] accel/tcg: Add tcg call flags to plugins helpers Richard Henderson
2021-06-01 15:00 ` [PATCH v7 06/27] tcg: Store the TCGHelperInfo in the TCGOp for call Richard Henderson
2021-06-01 15:00 ` [PATCH v7 07/27] tcg: Add tcg_call_func Richard Henderson
2021-06-01 15:00 ` [PATCH v7 08/27] tcg: Build ffi data structures for helpers Richard Henderson
2021-06-01 15:00 ` [PATCH v7 09/27] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-06-02 17:59 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 10/27] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-06-01 15:00 ` [PATCH v7 11/27] tcg/tci: Use ffi for calls Richard Henderson
2021-06-02 10:31 ` Alex Bennée
2021-06-01 15:00 ` [PATCH v7 12/27] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-06-19 15:50 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 13/27] tcg/tci: Emit setcond before brcond Richard Henderson
2021-06-19 15:50 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 14/27] tcg/tci: Remove tci_write_reg Richard Henderson
2021-06-01 15:00 ` [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-06-12 10:21 ` Philippe Mathieu-Daudé
2021-06-12 15:40 ` Richard Henderson
2021-06-19 17:48 ` Philippe Mathieu-Daudé
2021-06-19 18:05 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 16/27] tcg/tci: Implement goto_ptr Richard Henderson
2021-06-12 9:45 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 17/27] tcg/tci: Implement movcond Richard Henderson
2021-06-01 15:00 ` [PATCH v7 18/27] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-06-01 15:00 ` [PATCH v7 19/27] tcg/tci: Implement extract, sextract Richard Henderson
2021-06-01 15:00 ` Richard Henderson [this message]
2021-06-01 15:01 ` [PATCH v7 21/27] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-06-01 15:01 ` [PATCH v7 22/27] tcg/tci: Implement add2, sub2 Richard Henderson
2021-06-12 9:36 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 23/27] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
2021-06-02 18:01 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 24/27] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" Richard Henderson
2021-06-12 9:24 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 25/27] tcg/tci: Remove the qemu_ld/st_type macros Richard Henderson
2021-06-02 18:03 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 26/27] tcg/tci: Use {set,clear}_helper_retaddr Richard Henderson
2021-06-12 9:24 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 27/27] tests/tcg: Increase timeout for TCI Richard Henderson
2021-06-02 9:26 ` Alex Bennée
2021-06-01 15:30 ` [PATCH v7 00/27] TCI fixes and cleanups no-reply
2021-06-19 17:42 ` Philippe Mathieu-Daudé
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